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ltm4641 1 4641f typical application features description 38v, 10a dc/dc module regulator with advanced input and load protection the ltm ? 4641 is a switch mode step-down dc/dc module ? (micromodule) regulator with advanced input and load protection features. trip detection thresholds for the following faults are customizable: input undervoltage, overtemperature, input overvoltage and output overvolt - age. select fault conditions can be set for latchoff or hysteretic restart responseor disabled. included in the package are the switching controller and housekeeping ics, power mosfets, inductor, overvoltage drivers, biasing circuitry and supporting components. operating from input voltages of 4v to 38v (4.5v start-up), the device supports output voltages from 0.6v to 6v, set by an external resis - tor network remote sensing the point-of-loads voltage. the ltm4641s high efficiency design can deliver up to 10a continuous current with a few input and output ca - pacitors. the regulators constant on-time current mode control architecture enables high step-down ratios and fast response to transient line and load changes. the ltm4641 is offered in a 15mm 15mm 5.01mm rohs compliant bga package with pb-free finish. applications n wide operating input voltage range: 4.5v to 38v n 10a dc typical, 12a peak output current n output range: 0.6v to 6v n 1.5% maximum total output dc voltage error n differential remote sense amplifier for pol regulation n internal temperature, analog indicator output n overcurrent foldback and overtemperature protection n current mode control/fast transient response n parallelable for higher output current n selectable pulse-skipping operation n soft-start/voltage tracking/pre-bias start-up n 15mm 15mm 5.01mm bga package input protection n uvlo, overvoltage shutdown and latchoff thresholds n n-channel overvoltage power-interrupt mosfet driver n surge stopper capable with few external components load protection n robust, resettable latchoff overvoltage protection n n-channel overvoltage crowbar power mosfet driver n ruggedized electronics n avionics and industrial equipment l , lt, ltc, ltm, module, burst mode, linear technology and the linear logo are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5847554, 6100678, 6304066, 6580258, 6677210. v out (200mv/div) 4s/div tested at worst-case condition: no load 4641 ta01b short-circuit applied 1.1v out peak crowbar (5v/div) 4 3 2 1 v inl , v inh (25v/div) 1v load protected from m top short-circuit at 38v in module regulator with input disconnect and fast crowbar output overvoltage protection + iovretry v ing v ingp v inh sw mcb** m bot m top msp* 4 3 1 2 v out crowbar v osns + v osns ? gnd ov pgm v inl f set 750k 5.6m 4641 ta01a sgnd connects to gnd internal to module regulator msp: (optional) series-pass overvoltage power interrupt mosfet, nxp psmn014-60ls mcb: (optional) output overvoltage crowbar mosfet, nxp ph2625l * ** 5.49k 5.49k ltm4641 10f 50v 2 uvlo intv cc drv cc run 10nf track/ss ovlo fcb latch sgnd 100f 3 v out 1v 10a 100f 50v v in 4v to 38v 4.5v start-up load
ltm4641 2 4641f table of contents features .................................................... 1 applications ................................................ 1 typical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 typical performance characteristics ................... 8 pin functions .............................................. 10 simplified block diagram ............................... 15 decoupling requirements ............................... 15 operation ................................................... 16 introduction ............................................................ 16 motivation ............................................................... 16 power module regulator reliability ...................... 16 overview ................................................................. 16 applications informationpower supply features . 17 power (v inh ) and bias (v inl ) input pins ................. 17 switching frequency (on time) selection and voltage dropout criteria (achievable v in -to-v out step-down ratios) .................................................. 18 setting the output voltage; the differential remote sense amplifier ...................................................... 21 input capacitors ..................................................... 23 output capacitors and loop stability/loop compensation ......................................................... 23 pulse-skipping mode vs forced continuous mode 24 soft-start, rail-tracking and start-up into pre-bias .................................................................. 24 intv cc and drv cc ................................................. 27 1v ref ...................................................................... 28 temp, otbh and overtemperature protection ........ 28 applications informationinput protection features .................................................... 29 input monitoring pins: uvlo, iovretry, ovlo .... 29 start-up/shutdown and run enable; power-on reset and timeout delay time ......................................... 31 applications informationload protection features .................................................... 32 overcurrent foldback protection ............................ 32 power good indicator and latching output overvoltage protection ........................................... 32 power-interrupt mosfet (msp), crowbar pin and output crowbar mosfet (mcb) ........................ 33 fast output overvoltage comparator threshold ..... 34 applications informationemi performance ........ 35 the switching node: sw pin .................................. 35 applications informationmultimodule parallel operation ................................................... 36 applications informationthermal considerations and output current derating ............................ 38 thermal considerations and output current derating .................................................................. 38 applications informationoutput capacitance table ........................................................ 45 applications informationsafety and layout guidance ................................................... 46 safety considerations ............................................. 46 layout checklist/example ...................................... 46 typical applications ...................................... 48 appendices ................................................ 55 appendix a. functional block diagram and features quick reference guide ............................................ 55 appendix b. start-up/shutdown state diagram ..... 56 appendix c. switching frequency considerations and usage of r fset ........................................................ 57 appendix d. remote sensing in harsh environments .......................................................... 58 appendix e. inspiration for pulse-skipping mode operation ................................................................ 59 appendix f. adjusting the fast output overvoltage comparator threshold ............................................ 59 package description ..................................... 62 package photo ............................................ 62 package description ..................................... 63 typical application ....................................... 64 related parts .............................................. 64
ltm4641 3 4641f pin configuration absolute maximum ratings terminal voltages v inl , v inh , sw, f set ............................... C0.3v to 40v v out ...................................................... C0.3v to 9.2v v ing ............................................ C0.3v to v inh + 20v intv cc , drv cc , run, track/ss, pgood, crowbar, hyst .................................... C0.3v to 6v fcb, tmr ................................ -0.3v to intv cc + 0.3v comp ................................................... C0.3v to 2.7v v osns + , v orb + ...................................... C0.6v to 9.7v v osns C , v orb C .......... v osns + C 2.7v to v osns + + 0.3v otbh, uvlo, iovretry, ovlo, latch .................................................... C0.3v to 7.5v temp, ov pgm ....................................... C0.3v to 1.5v terminal currents intv cc (continuous) ....................................... C30ma intv cc (continuous; crowbar sourcing 15ma) ............................................... C15ma crowbar (continuous) .................................. C15ma v ingp (continuous) ........................... C50ma to 15ma 1v ref (continuous) ................................ C1ma to 1ma internal operating temperature range (note 2) e- and i-grades .................................. C40c to 125c mp-grade .......................................... C55c to 125c storage temperature range .................. C55c to 125c peak package body temperature (smt reflow) ... 245c (note 1) sw bga package 144-lead (15mm 15mm 5.01mm) top view gnd gnd gnd gnd 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a ov pgm crowbar temp iovretry 1v ref ovlo hyst uvlo sgnd v orb ? v orb + v osns ? v osns + drv cc sgnd v inl f set latch runtmrotbh comp pgood track/ss v inh v out v ingp v ing sgnd intv cc fcb t jmax = 125c, jctop = 11c/w, jcbottom = 2.5c/w jb = 3c/w, ja = 10.4c/w values determined per jesd51-12 weight = 2.9 grams order information lead free finish tray part marking* package description temperature range (note 2) ltm4641ey#pbf ltm4641ey#pbf ltm4641y 144-lead (15mm 15mm 5.01mm) bga C40c to 125c ltm4641iy#pbf ltm4641iy#pbf ltm4641y 144-lead (15mm 15mm 5.01mm) bga C40c to 125c ltm4641mpy#pbf ltm4641mpy#pbf ltm4641y 144-lead (15mm 15mm 5.01mm) bga C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
ltm4641 4 4641f electrical characteristics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = v inh = v inl = 28v, per the typical application shown in figure 45, unless otherwise noted. symbol parameter conditions min typ max units v in input dc voltage l 4.5 38 v v out output voltage range use r set1a = r set1b 8.2k. r fset values recommended in table 1 l 0.6 6 v v out(dc) output voltage, total variation with line and load, and prior to uvlo 4.5v v in 38v, 0a i out 10a v in = 4v (ramped down from 4.5v), i out = 0a l l 1.773 1.773 1.800 1.800 1.827 1.827 v v input specifications v run(on,off) run on/off threshold run rising, turn on run falling, turn off l l 0.8 1.25 1.15 2 v v i run(on) run pull-up current v run = 0v v run = 3.3v l l C580 C220 C520 C165 C460 C110 a a i run(off) run pull-down current, switching inhibited v run = 3.3v, uvlo = 0v (m hyst on) 1 na v inl(uvlo) v inl undervoltage lockout v inl rising v inl falling hysteresis l l l 3.5 300 4.2 3.8 400 4.5 4 v v mv i inrush(vinh) input inrush current through v inh , at start-up c ss = open 230 ma i q(vinh) power stage bias current (i vinh ) at no load i out = 0a and: fcb 0.84v (pulse-skipping mode) fcb 0.76v (forced continuous mode) shutdown, run = 0 8 29 0.2 ma ma ma i q(vinl) control bias current (i vinl ) intv cc connected to drv cc and: v in = 28v, i out = 0a v in = 28v, i out = 10a v in = 28v, shutdown, run = 0 14.5 15.5 5 ma ma ma i s(vinh) power stage input current (i vinh ) at full load i out = 10a and: v in = 4.5v v in = 28v v in = 38v 4.65 790 590 a ma ma output specifications i out(dc) output continuous current range (note 3) l 0 10 a ?v out(line) /v out line regulation accuracy v in from 4.5v to 38v, i out = 0a l 0.02 0.15 % ?v out(load) /v out load regulation accuracy i out from 0a to 10a (note 3) l 0.04 0.15 % v out(ac) output voltage ripple amplitude i out = 0a 16 mv p-p f s output voltage ripple frequency i out = 0a i out = 10a 290 330 khz khz v out(start) turn-on overshoot i out = 0a 10 mv t start v in -to-v out start-up time run electrically open circuit, time between application of v in to v out becoming regulated, ov pgm = 1.5v, c tmr = c ss = open 3 ms t run(on-delay) run-to-v out turn-on response time v in established, (tmr-set por time expired) time between run releasing from gnd to pgood going logic high, c ss = open, ov pgm = 1.5v 175 400 s ?v out(ls) peak deviation for dynamic load step i out from 0a to 5a at 5a/s i out from 5a to 0a at 5a/s 40 40 mv mv t settle(ls) settling time for dynamic load step i out from 0a to 5a at 5a/s i out from 5a to 0a at 5a/s 20 20 s s
ltm4641 5 4641f electrical characteristics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = v inh = v inl = 28v, per the typical application shown in figure 45, unless otherwise noted. symbol parameter conditions min typ max units i out(pk) output current limit 5.1k pull-up from pgood to 5v source, i out ramped up until v out below pgood lower threshold, pgood pulls logic low 24 a i vinh(iout_short) power stage input current during output short circuit v out electrically shorted to gnd 45 ma control section v fb differential feedback voltage from v osns + to v osns C i out = 0a l 591 600 609 mv i track/ss track/ss pull-up current v track/ss = 0v C0.45 C1 a v fcb fcb threshold 0.76 0.8 0.84 v i fcb fcb pin current v fcb = 0.8v 0 1 a t on(min) minimum on-time (note 4) 43 75 ns t off(min) minimum off-time (note 4) 220 300 ns v osns(dm) remote sense pin-pair differential mode input range valid differential v osns + -to- v osns C range (use r set1a = r set1b 8.2k) l 0 2.7 v v osns(cm) remote sense pin-pair common mode input range valid v osns C common mode range valid v osns + common mode range (use r set1a = r set1b 8.2k) l l C0.3 3 v v r in(vosns + ) input resistance v osns + to gnd 16318 16400 16482 intv cc , drv cc , 1v ref v intvcc internal v cc voltage 6v v in 38v, intv cc not connected to drv cc , drv cc = 5.3v l 5.1 5.3 5.4 v ?v intvcc(load) v intvcc intv cc load regulation run = 0v, intv cc not connected to drv cc , drv cc = 5.3v and: i intvcc varied from 0ma to C20ma i intvcc varied from 0ma to C30ma C0.7 C1 2 3 % % v intvcc(lowline) intv cc voltage at low line v in = 4.5v, r set1a = r set1b = 0 (~0.6v out , r fset value recommended in table 1) l 4.2 4.3 v drv cc(uvlo) drv cc undervoltage lockout drv cc rising drv cc falling l l 3.9 3.2 4.05 3.35 4.2 3.5 v v i drvcc drv cc current intv cc not connected to drv cc , drv cc = 5.3v, r set1a , r set1b and r set2 setting v out to: 1.8v out , r fset = 2m, 0a i out 10a 6.0v out , r fset = open, 0a i out 10a (use r set1a = r set1b 8.2k) 11 20 18 27 ma ma v 1vref(dc) 1v ref dc voltage regulation i 1vref = 0ma i 1vref = 1ma l l 0.985 0.980 1.000 1.000 1.015 1.020 v v pgood output v pgood(th) power good window, logic state transition thresholds ramping differential v osns + C v osns C voltage: up, pgood goes logic low high up, pgood goes logic high low down, pgood goes logic low high down, pgood goes logic high low 533 645 621 525 556 660 644 540 579 675 667 555 mv mv mv mv v pgood(hyst) hysteresis differential v osns + C v osns C voltage returning 8 16 24 mv v pgood(vol) logic-low output voltage i pgood = 5ma l 75 400 mv t pgood(delay) pgood logic-low blanking time delay between differential v osns + C v osns C voltage exiting pgood valid window to pgood going logic low (note 4) 12 s
ltm4641 6 4641f electrical characteristics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = v inh = v inl = 28v, per the typical application shown in figure 45, unless otherwise noted. symbol parameter conditions min typ max units power-interrupt mosfet drive v ving gate drive voltage for power- interrupt mosfet, msp v in = 4.5v, 0a i out 10a, v ing sourcing 1a v in = 28v, 0a i out 10a, v ing sourcing 1a v in = 38v, 0a i out 10a, v ing sourcing 1a v in = 4v (ramped down from 4.5v), i out = 0a, v ing sourcing 1a l l l l 11.5 35 45 10.5 13.3 38.4 48.4 11.5 15.5 41 51.5 14.2 v v v v i ving(up) v ing pull-up current v ing tied to v ingp , and: v in = 4.5v, v ing pulled to 6.5v v in = 28v, v ing pulled to 30v l l 350 425 475 550 600 675 a a i ving_down(crowbar active,crowbar inactive) v ing pull-down current v ing tied to v ingp , pulled to 33v, and: run pulled to 0v (crowbar inactive) ov pgm pulled to 0v (crowbar active) l l 3 24 20 27 30 30 ma ma t ving(ovp_delay) v ing ovp pull-down delay ov pgm driven from 650mv to 550mv, v ing discharge response time l 1.3 2.6 s i vingp(leak) zener diode leakage current v ingp driven to (v inh + 10v) 1 na v ingp(clamp) zener diode breakdown voltage v ingp -to-v inh differential voltage; i vingp = 5ma 15 v fault pins and functions v ovpgm default output overvoltage program setting ov pgm electrically open circuit l 650 666 680 mv i ovpgm(up) ov pgm pull-up current ov pgm = 0v l C2.07 C2 C1.91 a i ovpgm(down) ov pgm pull-down current ov pgm = 1v l 0.945 1 1.06 a ovp th output overvoltage protection inception threshold ramping up differential v osns + -to-v osns C voltage until crowbar outputs logic high l 647 666 683 mv ovp err output overvoltage protection inception error difference between ovp th and v ovpgm (ovp th -v ovpgm ) l C12 0 12 mv t crowbar(ovp_delay) crowbar response time ovp gm driven from 650mv to 550mv l 400 500 ns v crowbar(oh) crowbar output, active high voltage ovp gm pulled to 0v and: i crowbar = C100a, i intvcc = C20ma i crowbar = C4ma, i intvcc = C20ma l l 4.3 4.2 4.65 4.55 5 4.9 v v v crowbar(ol) crowbar output, passive low voltage i crowbar = 1a l 260 500 mv v crowbar(overshoot) crowbar peak voltage overshoot at v inl start-up and shutdown v inl ramped up from/down to 0v l 550 900 mv v crowbar(th) crowbar latchoff threshold crowbar ramped up until hyst goes logic low l 1.4 1.5 1.6 v v temp temp voltage run = 0v, t a = 25c run = 0v, t a = 125c (see figure 10 for reference) 950 980 585 1010 mv mv ot th(inception) temp overtemperature inception threshold ramping temp downward until hyst outputs logic low l 428 438 448 mv ot th(recover) temp overtemperature recovery threshold ramping temp upward until hyst outputs logic high l 501 514 527 mv uvov th uvlo/ovlo/iovretry undervoltage/overvoltage inception thresholds ramping uvlo, ovlo or iovretry positive until hyst toggles its state l 488 500 512 mv
ltm4641 7 4641f electrical characteristics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = v inh = v inl = 28v, per the typical application shown in figure 45, unless otherwise noted. symbol parameter conditions min typ max units t uvovd uvlo/ovlo/iovretry/ temp response time 50mv overdrive (all pins) 5mv overdrive, uvlo/ovlo/iovretry pins only (note 4) l 50 25 125 100 500 s s i uvov input current of uvlo, ovlo and iovretry uvlo = 0.55v or ovlo = 0.45v or iovretry = 0.45v l 30 na v housekeeping(uvlo) housekeeping circuitry uvlo voltage on intv cc , intv cc rising (note 4) hysteresis, intv cc returning (note 4) 1.9 5 2 25 2.1 50 v mv v hyst(switching on) hyst voltage (m hyst off, run logic high) run electrically open circuit run = 1.8v l l 4.9 1.85 5.1 2.1 5.25 2.35 v v v hyst(switching off, run) hyst voltage (m hyst off, run logic low) run = 0v l 170 350 480 mv v hyst(switching off, fault) hyst voltage, switching action inhibited (m hyst on) uvlo < uvov th or ovlo > uvov th or iovretry > uvov th or temp < ot th(inception) or crowbar > v crowbar(th) or drv cc < drvcc uvlo(falling) (see figures 62, 63) l 30 65 mv tmr uoto timeout and power-on reset period c tmr = 1nf, time from fault clearing to hyst being released by internal circuitry l 5 9 14 ms v latch(ih) latch clear threshold input high l 1.2 v v latch(il) latch clear threshold input low l 0.8 v i latch latch input current v latch = 7.5v l 1 a i tmr(up) tmr pull-up current v tmr = 0v l C1.2 C2.1 C2.8 a i tmr(down) tmr pull-down current v tmr = 1.6v l 1.2 2.1 2.8 a v tmr(dis) timer disable voltage referenced to intv cc l C180 C270 mv otbh vil otbh low level input voltage l 0.4 v otbh vz otbh pin voltage when left electrically open circuit C10a i otbh 10a l 0.6 0.9 1.2 v i otbh(max) maximum otbh current otbh electrically shorted to sgnd l 30 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. the ltm4641 sw absolute maximum rating of 40v is verified in ate by regulating v out while at 40v in , in a controlled manner guaranteed to not affect device reliability or lifetime. static testing of sw leakage current at 40v in is performed at control ic wafer level only. note 2: the ltm4641 is tested under pulsed load conditions such that t j t a . the ltm4641e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4641i is guaranteed over the C40c to 125c operating junction temperature range. the ltm4641mp is tested and guaranteed over the full C55c to 125c operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: see output current derating curves for different v in , v out and t a . note 4: 100% tested at wafer level only.
ltm4641 8 4641f typical performance characteristics pulse-skipping vs forced continuous mode efficiency, 28v in to 3.3v out 1v transient response, 38v in 1v transient response, 4.5v in 3.3v transient response, 28v in to 3.3v out output start-up, no load efficiency vs load current at 36v in efficiency vs load current at 6v in efficiency vs load current at 24v in efficiency vs load current at 12v in (figure 45 circuit with r fset per table 1 and r set1a , r set1b and r set2 per table 2, unless otherwise noted) output current (a) 0 60 efficiency (%) 65 75 80 85 95 1 5 7 4641 g01 70 90 4 9 10 2 3 6 8 6.0v out 5.0v out 3.3v out 2.5v out 1.8v out 1.5v out 1.2v out 1.0v out 0.9v out output current (a) 0 60 efficiency (%) 65 75 80 85 95 1 5 7 4641 g02 70 90 4 9 10 2 3 6 8 6.0v out 5.0v out 3.3v out 2.5v out 1.8v out 1.5v out 1.2v out 1.0v out 0.9v out output current (a) 0 60 efficiency (%) 65 75 80 85 95 1 5 7 4641 g03 70 90 4 9 10 2 3 6 8 6.0v out 5.0v out 3.3v out 2.5v out 1.8v out 1.5v out 1.2v out 1.0v out 0.9v out output current (a) 0 60 efficiency (%) 65 75 80 85 95 1 5 7 4641 g04 70 90 4 9 10 2 3 6 8 3.3v out 2.5v out 1.8v out 1.5v out 1.2v out 1.0v out 0.9v out output current (a) 0.001 efficiency (%) 50 60 70 10 4641 g05 40 30 0 10 0.01 0.1 1 20 90 80 fcb = intv cc (pulse-skipping) fcb = sgnd forced continuous v out 50mv/div ac-coupled i out 2.5a/div 20s/div 0a to 5a load steps at 5a/s front page circuit with ov pgm = open circuit 4641 g06 v out 50mv/div ac-coupled i out 2.5a/div 20s/div 4641 g07 0a to 5a load steps at 5a/s front page circuit with ov pgm = open circuit v out 50mv/div ac-coupled i out 2.5a/div 20s/div 4641 g08 0a to 5a load steps at 5a/s figure 46 circuit v out 1v/div i in 200ma/div run 5v/div 800s/div 4641 g09 v in = 24v c in(mlcc) = 2 10f x7r
ltm4641 9 4641f output start-up, 10a load (figure 45 circuit with r fset per table 1 and r set1a , r set1b and r set2 per table 2, unless otherwise noted) typical performance characteristics start-up with v inh shorted to sw node, 1v out(nom) start-up with v inh shorted to sw node, 3.3v out(nom) autonomous restart with v inh shorted to sw node, 3.3v out(nom) paralleled modules, current- sharing performance. cf. figure 66 circuit. 28v in control ic bandgap and 1v ref voltages vs temperature. 28v in output start-up, pre-bias condition output short-circuit, no initial load output short-circuit, 10a initial load v out 1v/div i in 1a/div run 5v/div 800s/div 4641 g10 v in = 24v c in(mlcc) = 2 10f x7r v out 1v/div i in 200ma/div i load 1ma/div run 5v/div 800s/div 4641 g11 v in = 24v c in(mlcc) = 2 10f x7r v out 1v/div i in 1a/div 20s/div 4641 g12 v in = 24v c in(mlcc) = 2 10f x7r v out 1v/div i in 1a/div 20s/div 4641 g13 v in = 24v c in(mlcc) = 2 10f x7r v in 20v/div v inh 2v/div crowbar 5v/div v out 200mv/div 400s/div 4641 g14 front page circuit with v inh short circuited to sw prior to power-up. applying up to 38v in . no load v in 10v/div v inh 5v/div crowbar 5v/div v out 1v/div 800s/div 4641 g15 figure 46 circuit with v inh short circuited to sw prior to power-up. applying up to 38v in . no load v in 10v/div v inh 10v/div crowbar 5v/div v out 1v/div 100ms/div 4641 g16 figure 46 circuit, short circuiting v inh to sw in situ, operating at 38v in and no load. latch connected to intv cc and c tmr = 47nf total output current (a) 0 8 10 12 16 4641 g17 6 4 4 8 12 20 2 0 ?2 module output current (a) u1 i out u2 i out junction temperature (c) ?75 0.594 v fb bandgap voltage (v) 1v ref voltage (v) 0.596 0.600 0.602 0.604 ?25 25 50 150 4641 g18 0.598 ?50 0 75 100 125 0.606 0.994 0.996 1.000 1.002 1.004 0.998 1.006 v 1vref(dc) v fb
ltm4641 10 4641f pin functions sgnd (a1-a3; b1-b3; c1-c4; k1, k3; l3; m1-m3): signal ground pins. this is the return ground path for all analog control and low power circuitry. sgnd is tied to gnd in - ternal to the module regulator in a manner that promotes the best internal signal integritytherefore, sgnd should not be connected to gnd in the users pcb layout. see the layout checklist/example section of the applications information section for more information pertaining to sgnd and layout. all sgnd pins are electrically connected to each other, internally. hyst (a4): input undervoltage hysteresis programming pin. normally used as an output, but can be used as an input. if the ltm4641s inherent, default undervoltage lockout (uvlo) settings are satisfactory, 4.5v in(rising, max) and 4v in(falling, max) , hyst can be left electrically open circuit. see the applications information section to customize the ltm4641s uvlo thresholds. hyst is a logic-high output with moderate pull-up strength that commands ltm4641s internal control ic to regulate the modules output voltage when conditions on the run, uvlo, ovlo, iovretry, temp, crowbar, intv cc and drv cc pins permit it (any recent latchoff events notwith - standing, otherwise otbh and latch can also play a role). when a fault condition is detected, internal circuitry (m hyst ; see figure 1) drives hyst logic low and the ltm4641s output is turned off. hyst can be used as a fault-indicator. see the applications information section. hyst is pulled low when the run pin is pulled low, via an internal schottky diode. hyst can be driven low by external open-collector/open-drain circuitry directlyas an alternate to the run pin interface. however, external circuitry should never drive hyst high, since doing so (indiscriminately) could cause thermal overstress to m hyst , when m hyst is on. temp (a5): power stage temperature indicator and overtemperature detection pin. when left electrically open circuit, temps voltage varies according to an internal ntc (negative temperature coefficient) thermistor, residing in close proximity to ltm4641s power stage. when temp falls below 438mv (corresponding to a thermistor and power stage temperature of ~145c), the ltm4641 pulls hyst low to inhibit regulation of its output voltage. hyst may be deasserted when temp subsequently exceeds 514mv (nominally corresponding to a cool-off hysteresis of ~10c), depending on the otbh setting. (see otbh and the applications information section.) to disable the module regulators overtemperature shutdown feature, connect the temp and 1v ref pins. the thermal shutdown inception threshold can also be modi - fied, see the applications information section. iovretry (a6): nonlatching input overvoltage threshold programming pin. the ltm4641 pulls hyst low to inhibit regulation of its output voltage when iovretry exceeds 0.5v. the ltm4641 can resume switching action when iovretry is below 0.5v. if no nonlatching input overvoltage shutdown behavior is desired, connect this pin to sgnd. do not leave this pin open circuit. gnd (a7-a12; b6-b8, b11-b12; c7-c8; d6-d8; e1-e8; f1-f12; g1-g12; h3-h9, h11-h12; j5-j12; k5-k6, k11- k12; l4-l6; m4-m6): power ground pins for input and output returns. see the layout checklist/example section of the applications information section. all gnd pins are electrically connected to each other, internally. uvlo (b4): input undervoltage lockout programming pin. the ltm4641 pulls hyst low to inhibit regulation of its output voltage whenever uvlo is less than 0.5v. the ltm4641 can resume switching action when uvlo exceeds 0.5v. do not leave this pin open circuit. if the ltm4641s default uvlo settings are used, 4.5v in(rising, max) and 4v in(falling, max) , then the uvlo pin should be electrically connected to 1v ref or intv cc . otherwise, see hyst and the applications information section for using a resistor-divider network to implement personalized uvlo rising and uvlo falling settings. ovlo (b5): input overvoltage latchoff programming pin. ltm4641 pulls hyst low to inhibit regulation of its output voltage when ovlo exceeds 0.5v. if ovlo subsequently falls below 0.5v, the modules output remains latched off; the ltm4641 cannot resume regulation of the output voltage until either the latch pin is toggled high or v inl is power cycled. if input overvoltage latchoff behavior is not desired, electrically short this pin to sgnd. do not leave this pin open circuit.
ltm4641 11 4641f pin functions crowbar (b9): crowbar output pin. normally logic low, with moderate pull-down strength to sgnd. when an output overvoltage (oov) condition is detected, the ltm4641s fast oov comparator pulls crowbar logic high through a series-connected internal diode. if utilizing ltm4641s oov feature, crowbar should connect to the gate of a logic-level n-channel mosfet configured to crowbar the modules output voltage (mcb, in figure 1). furthermore, the ltm4641 latches off its output when crowbar nominally exceeds 1.5v and latches hyst logic low (see hyst). if not using the oov protection features of the ltm4641, leave crowbar electrically open circuit. ov pgm (b10): output overvoltage threshold programming pin. the voltage on this pin sets the trip threshold for the inverting input pin of ltm4641s fast oov comparator. when left electrically open circuit, resistors internal to the ltm4641 nominally bias ov pgm to 666mv (ov pth )11% above the nominal v fb feedback voltage (600mv) that the control loop strives to present to the noninverting input pin of ltm4641s fast oov comparator. the aforementioned voltages correspond proportionally to the modules oov inception threshold and v out s nominal voltage of regula - tion, respectively. altering the ov pgm voltage provides a means to adjust the oov threshold; its dc-bias setpoint can be tightened with simple connections to external components (see the applications information section). trace route lengths and widths to this sensitive analog node should be minimized. minimize stray capacitance to this node unless altering the oov threshold as described in the applications information section and appendix f . latch (c5): latchoff reset pin. when a latchoff fault oc - curs, the ltm4641 turns off its output and latches m hyst on to indicate a fault condition has occurred (see hyst). to configure the ltm4641 for latched off response to latchoff faults, connect latch to sgnd. as long as latch is logic low, the ltm4641 will not unlatch. regulation can be re - sumed by cycling v inl or by toggling latch from logic low to high. it is also permissible to connect latch to intv cc ; this configures the ltm4641 for autonomous restart with a timeout delay (programmed by c tmr see tmr). if no latchoff faults are present when latch transitions from logic low to logic high, the ltm4641 immediately un - latches. if any latchoff fault is present when latch is logic high, a timeout delay timing requirement is imposed: the ltm4641 will not unlatch until all latchoff fault-monitoring pins meet operationally valid states for the full duration of the timeout delay. if latch becomes logic low before that timeout delay has expired, the ltm4641 remains latched off and the timeout delay is reset. unlatching the ltm4641 can be reattempted by pulling latch logic high at a later time. the following are latchoff fault conditions: ? crowbar activates (see crowbar) ? input latchoff overvoltage fault (see ovlo) ? latchoff overtemperature fault (when otbh is logic low; see temp and otbh) latch is a high impedance input and must not be left elec - trically open circuit. latch can be driven by a controller in intelligent systems: a reasonable implementation for unlatching the ltm4641 is to pull latch logic high for the maximum anticipated timeout delay timeafter which, hyst can be observed to indicate whether the ltm4641 has become unlatched. 1v ref (c6): buffered 1v reference output pin. minimize capacitance on this pin, to assure the ov pgm and temp pins are operational in a timely manner at power-up. 1v ref should never be externally loaded except as explained in the applications information section. v out (c9-c12; d9-d12; e9-e12): power output pins of the ltm4641 dc/dc converter power stage. all v out pins are electrically connected to each other, internally. apply output load between these pins and the gnd pins. it is recommended to place output decoupling capacitance directly between these pins and the gnd pins. review table 9. see the layout checklist/example section of the applications information section. v orb + (d1): v osns + readback pin. this pin connects to v osns + internal to the module regulator. it is recommended to route this pin (differentially with v orb C ) to a test point so as to allow the user a way to confirm the integrity of
ltm4641 12 4641f pin functions the remote-sense connections prior to powering up the ltm4641. v orb + can also be connected as a redundant feedback connection to v osns + on the users motherboard. v orb C (d2): v osns C readback pin. this pin connects to v osns C internal to the module regulator. it is recommended to route this pin (differentially with v orb + ) to a test point so as to allow the user a way to confirm the integrity of the remote-sense connections prior to powering up the ltm4641. v orb C can also be connected as a redundant feedback connection to v osns C on the users motherboard. otbh (d3): overtemperature behavior programming pin. when an overtemperature condition is detected (see temp), hyst pulls logic low to inhibit switching. if otbh is connected to sgnd, the ltm4641 latches hyst low. if otbh is left floating, output voltage regulation can resume when the overtemperature event clears. tmr (d4): timeout delay timer and power-on reset (por) programming pin. connect a capacitor (c tmr ) from tmr to sgnd to program the por and timeout delay time of the ltm4641; 9ms delay time per nanofarad of capacitance. the minimum delay time is ~90s, when tmr is left electrically open circuit. even though they use the same capacitor, the power-on reset and timeout delay timers operate independently of each other. any nonlatching fault or latching fault will reset the respective timer to the full delay time without impacting the other timer. the timeout delay time programmed by a c tmr capacitor can be negated by pulling tmr to intv cc . run (d5): run (on/off) control pin. a run pin voltage below 0.8v will turn off the module. a voltage above 2v will command the module to turn on, if hyst is not as- serted low by m hyst . the ltm4641 contains a moderate (10k) pull-up resistor from hyst to intv cc , and a pull-up schottky diode from run to hyst (see figure 1). when run is pulled logic low, hyst is pulled logic low via the internal schottky diode. run is compatible with direct- drive (totem-pole output drive) as well as open-collector/ open-drain interfaces. v osns + (h1): positive input to the remote sense differ - ential amplifier. this pin connects to the positive side of the output voltage remote sense point (v out potential) via a resistor (r set1a ). when regulating the output voltage, the ltm4641 control loop drives the differential voltage between v osns + and v osns C to the lesser of track/ ss and 0.6v. v osns + is connected to v orb + internal to the module (see v orb + ). a resistor may be needed from v osns + to v osns C for some output voltage settings. (see the applications information section: setting the output voltage.) minimize stray capacitance to this pin to protect the integrity of the output voltage feedback signal. v osns C (h2): negative input to the remote sense dif - ferential amplifier. this pin connects to the negative side of the output voltage remote sense point (gnd potential) via a resistor (r set1b ). when switching action is on, the ltm4641 control loop drives the differential voltage between v osns + and v osns C to the lesser of track/ ss and 0.6v. v osns C is connected to v orb C internal to the module (see v orb C ). a resistor may be needed from v osns + to v osns C for some output voltage settings. (see the applications information section.) minimize stray ca - pacitance to this pin to protect the integrity of the output voltage feedback signal. sw (h10): switching node of the power stage. mainly used for testing purposes, however, one may optionally connect a snubber (series-configured capacitor c sw and resistor r sw ) from sw to gnd to reduce radiated emiin exchange for a minor compromise to power conversion efficiency. (see the applications information section.) comp (j1): current control threshold and error amplifier compensation point. the current comparator threshold of ltm4641s valley current mode control loopand corre - spondingly, the commanded trough of the power inductor currentincreases as this control voltage increases. it can be useful to make comp available for observation on a pcb via or test pad with an oscilloscope probe. however, stray capacitance and trace lengths to this sensitive analog node should be minimized. f set (j2): switching frequency setting and adjustment pin. this pin interfaces directly to the i on pin of ltm4641s internal control ic. current flow into the i on pin programs the on-time of the control loops one-shot timer and power control mosfet, m top . minimize stray capacitance and any tracelengths to this pin. for applications requiring regulated output voltages of 3v or less at any time including during voltage rail tracking,
ltm4641 13 4641f pin functions an on-time adjustment with a resistor to f set is required. otherwise, f set can be left open circuit. see the applica - tions information section for details. v inl (j3): input voltage pin, low current for power control and logic bias. feeds ltm4641s internal 5.3v ldo (see intv cc ). apply input voltage bias between this pin and gnd. decouple to gnd with a capacitor (0.1f to 1f). this pin powers the heart of ltm4641s dc/dc controller and internal housekeeping ics. v inl bias cur - rent is within ~5ma of the sum of intv cc and crowbar loading currents. if using the advanced output overvoltage (oov) protection features of the ltm4641, connect v inl to either the drain of the external power-interrupt power mosfet, identified on the front page schematic as msp, or a separate input bias supply. if not making use of the advanced oov protection features, v inl and v inh can connect directly to the same input power source. ldo losses can be eliminated by connecting v inl , intv cc , and drv cc if a low power auxiliary ~5v rail is available to power the resulting node. (see the applications informa - tion section, figure 47 and figure 49.) drv cc (j4): power mosfet driver input power pin. drv cc is normally connected to intv cc . it must be kept within two diode drops (2 ? v be or ~1.2v at 25c) of intv cc . drv cc powers the internal mosfet driver that interfaces to the switching mosfets (m top and m bot ) within ltm4641s power stage. it is pinned out separately from intv cc to allow gate-driver current to be observed, and to allow an auxiliary ~5v to 6v bias supply to optionally provide the mosfet driver bias current. the intv cc /drv cc pin pair can be biased from up to 6v (absolute maximum) from an external supply with 50ma peak sourcing capability, to reduce the ltm4641s intv cc ldo losses (see applica - tions information section and figure 51). when drv cc is connected directly to intv cc , no bypass capacitance is needed except in rare applications where very fast output voltage ramp up is required (e.g., no soft-start capacitor on track/ss, or rail-tracking rails with sub-60s turn-on rise-time). otherwise, ~2.2f to 4.7f x7r mlcc local bypassing to gnd is recommended. higher impedance sources may require higher bypass capacitance, to mitigate drv cc sag during v out start-up. an undervoltage lockout detector monitors drv cc . hyst is pulled low and switching action is inhibited if drv cc is less than 4.2v rising (maximum) and 3.5v falling (maximum). fcb (k2): forced continuous/pulse-skipping mode opera - tion programming pin. connect this pin to sgnd to force continuous mode operation of the synchronous power mosfets (m top and m bot ) at all output load conditions. connect this pin to intv cc to enable pulse-skipping mode operation: the freewheeling power switching mosfet (m bot ) is turned off of to prevent reverse flow of output current (i out ) at light loads. see appendix e for more details. this is a high impedance input and must not be left electrically open circuit. intv cc (k4): internal 5.3v ldo output. ldo operates off of v inl . the intvcc rail biases low power control and housekeeping circuitry. intv cc is usually connected to drv cc to power the mosfet drivers interfacing to the switching power mosfets. no decoupling capacitance is needed on this pin unless it is being used to bias external circuitry (not common); do not apply more than 4.7f (20% tolerance) of external decoupling capacitance. the intv cc /drv cc pin pair can be overdriven by an external supply, from up to 6v (absolute maximum) with 50ma peak sourcing capability, to eliminate power losses otherwise incurred by the ltm4641s v inl -to-intv cc linear regulator (see the applications information section and figure 51). v inh (k7-10; l7-12; m7-8, 11-12): input voltage pin, high current to the power converter stage of the ltm4641. all v inh pins are electrically connected to each other internally. devote a large copper plane to connect as many of the v inh pins to each other as is feasible. this will help form a low impedance electrical connection between the input source and the ltm4641s power stage. it will also provide a thermal path for removing heat from the bga package and minimize junction temperature rise of the ltm4641 for a given application. if utilizing the advanced output overvoltage (oov) protec - tion features of the ltm4641, connect v inh to the source pin(s) of the external power-interrupt mosfet, identified on the front page schematic as msp, with a short wide trace, or preferably a small copper plane capable of adequately
ltm4641 14 4641f pin functions handling the input current to ltm4641s power stage. do not decouple the v inh pins with any bypass capacitance in this case. instead, place all decoupling capacitance directly between the drain of msp to gnd. if not utilizing the advanced oov protection features of the ltm4641, do decouple the v inh pins to gnd with local ceramic and bulk decoupling capacitance (see the applications information section). pgood (l1): output voltage power good indicator. this is an open-drain logic output pin that is pulled to ground when the output voltage (and accordingly, the divided-down representation of the output voltage, v fb , as presented to the control loop) is outside 10% of the nominal target for regulation. track/ss (l2): output voltage tracking and soft-start programming pin. this pin has a 1.0a pull-up current source, typical. a capacitor can be placed from this pin to sgnd to obtain an output voltage soft-start ramp-up rate whose turn-on time is 0.6ms per nanofarad of capacitance. alternatively, when a voltage is applied to track/ss through a resistor-divider network from another rail, the ltm4641 output is able to track the external voltage to satisfy coincident and ratiometric rail-voltage sequencing requirements. see the applications information section. v ing (m9): gate drive output pin. if utilizing the advanced output overvoltage (oov) protection features of the ltm4641, connect v ing to v ingp and to the gate of the external power-interrupt n-channel mosfet feeding v inh , identified on the front page schematic as msp; otherwise, leave this pin electrically open circuit. v ingp (m10): gate drive protection pin. if utilizing the ad - vanced oov protection features of the ltm4641, connect v ingp to v ing and to the gate of the external power-interrupt n-channel mosfet feeding v inh , msp; otherwise, leave this pin electrically open circuit.
ltm4641 15 4641f simplified block diagram decoupling requirements figure 1. simplified block diagram. cf. functional block diagram in appendix a , figure 62 symbol parameter conditions min typ max units c in(mlcc) + c in(bulk) external input capacitor requirement i out = 10a, 2 10f or 4 4.7f 20 f c out(mlcc) + c out(bulk) external output capacitor requirement i out = 10a, 3 100f or 6 47f 300 f + ? + 8.2k r set2 r c mcb m bot 10f c in(mlcc) 0.1f 2.2f c out(mlcc) v out 0.6v to 6v up to 10a v out 4v to 38v (4.5v start-up) c out(bulk) + c in(bulk) 8.2k 8.2k r set1b r set1a 4641 f01 v orb + v orb ? crowbar dashed boxes indicate optional components *r fset required for certain v in /v out combinations see applications information section sgnd connects to gnd internal to module, keep sgnd routes/planes separate from gnd, on motherboard sgnd v osns + v osns ? 8.2k enable fast output overvoltage comparator power control enable switching action constant on-time valley mode synchronous buck controller msp r fset * 1.3m 10k v fb to e/a gnd sw 15v zener v out v inh v ingp v ing v inl f set i on intv cc v in v in 0.8h m top m hyst hyst r hyst r tuv r buv r tov r mov r bov 3.48k 499k 1m 1v ref ntc uvlo iovretry ovlo temp otbh latch tmr fcb comp drv cc intv cc pgood protection comparators and fault latches osc ref c tmr c ss 4f track/ss 1v ref ov pgm run r tovpgm r bovpgm c ovpgm internal comp use r set1a = r set1b 8.2k r set2 required for v out > 1.2v r set2 not necessary for v out 1.2v v out = 0.6 1 + r set1a 8.2k + 2 ? r set1a r set2 ? ? ? ? ? ?
ltm4641 16 4641f operation introduction the ltm4641 contains a buck-topology regulator employ - ing a constant on-time current mode control scheme, including built-in power mosfet devices with fast switching speed and a power inductor. in its most basic configuration (see figure 45), the module operates as a standalone nonisolated switching mode dc/dc step-down power supply. it can provide up to 10a of output current with a few external input and output capacitors and output feedback resistors. the supported output voltage range is from 0.6v dc to 6v dc. the supported input voltage range is 4v to 38v, with a maximum start-up voltage of 4.5v (over temperature). power conversion from lower input voltages can be realized if an auxiliary bias supply is available to power ltm4641s control and housekeeping bias input pin, v inl . the ltm4641 simplified block diagram is found in figure 1. for a more detailed look, the functional block diagram is found in appendix a, figure 62. motivation pulsed loading conditions and abnormal disturbances within the electrical systems found in industrial, vehicle, aeronautic, and military applications can induce wildly varying voltage transients (surges) on what is nominally a 24v dc to 28v dc distributed bus (28v dc bus). the duration of such disturbances can extend for periods of time between a millisecond to a minute in length, with excursions sometimes reaching (or exceeding) 40v and falling below 6v. while switching buck regulators are of universal inter - est due to their compact size and ability to deliver dc/ dc power conversion at high efficiency, fmea (failure modes and effects analysis) leads one to believe that there is no way to reduce the severity rating and effects of an electrical short from the input source to the output loadhowever improbable. the ltm4641 challenges this notion by protecting the load from seeing excessive volt - age stress, even when its high side switching mosfet is short circuited. power module regulator reliability first and foremost, linear technology module products adhere to rigorous testing and high reliability control, fabrication, and manufacturing processesas is required of all its products. furthermore, as part of its commit - ment to excellence, the linear technology quality control program periodically updates its reliability data report for ltm4600 series products to include cumulative data obtained from ongoing and routine in-house testing relat - ing to operational life, highly accelerated stress, power and temperature cycling, thermal and mechanical shock, and much more. to view the latest report visit http://www. linear.com/docs/13557. the ltm4641 easily supports high step-down ratios with few external components. the additional protection features when implemented provide an extra degree of insurance beyond other module regulators. overview when configured as shown in figure 46, the ltm4641 can regulate an output voltage between 0.6v and 6v from an input voltage between 4v and 38v (4.5v in start-up, maximum). if an optional n-channel power mosfet, msp, is placed between the input power source (v in ) and the power stage input pins (v inh ), msps role becomes that of a resettable electronic power-interrupt switch. the gate of msp is operated by v ing , and its gate-to-source voltage is assured to be clamped by a built-in 15v zener diode accessed via v ingp . when switching action is engaged, v ing charges the gate of msp to nominally 10v above v inh potentialsuitable for driving a standard-logic mos - fetand msp becomes enhanced to pull v inh up to the input source supplys electrical potential. the switching regulator steps down v inh potential to v out when msp is on. when switching action is inhibited by pulling the run pin low or when a fault condition is detected by ltm4641s internal circuitrysuch as an output overvoltage (oov) conditionthe gate of msp is discharged and msp turns off. the input source supply is thus disconnected from ltm4641s power stage input (v inh ).
ltm4641 17 4641f applications informationpower supply features the operation of msp as a power interrupter provides a critical element of robust oov protection: it removes a means for input power to flow through a damaged power stage to any precious loads on the output voltage rail, even when input power is cycled. for even greater resilience to a short-circuit between v inh and the sw switching node of the power stage, an external logic-level n-channel power mosfet, mcb, is optionally placedin a crowbar configurationon the output of the power module. when an oov condition is detected, crowbar turns on mcb (within 500ns, maximum) to discharge the output capacitors and transform any residual energy in ltm4641s power stage into a trivial amount of heatenergy which would otherwise have only served to inject charge into (further pump up the voltage on) the output capacitors, where precious loads reside. the control and monitoring circuitry within the ltm4641 power module provide the following: ? fast, accurate, latching output overvoltage detector (<500ns response time, <12mv threshold error) ? n-channel output overvoltage crowbar power mosfet drive ? accurate (<2.4%) nonlatching and resettable latching input overvoltage shutdown thresholds ? n-channel overvoltage power-interrupt mosfet drive ? accurate (<2.4%) input uvlo rising and uvlo falling thresholds ? built-in and adjustable overtemperature shutdown protection, programmable for resettable latching or nonlatching (hysteretic restart) response ? analog temperature indicator output pin ? adjustable power-on reset and timeout delay time ? latchoff behavior that can be altered to instead provide autonomous restart after timeout delay time expires ? parallelable for higher output power ? differential remote sensing of pol voltage ? internal loop compensation ? output current foldback protection ? selectable pulse-skipping mode operation ? output voltage soft-start and rail tracking ? power-up into pre-biased conditions without sinking current from the output capacitors ? adjustable switching frequency ? power good indicator ? run enable pin novel and simple circuit implementations with ltm4641 and a few external components enable surge ride- through protection and overtemperature detection of a power-interrupt mosfet. (see figure 47, for example.) the aforementioned features enabled by ltm4641 are grouped by function and described in the remainder of the applications information section. power (v inh ) and bias (v inl ) input pins ltm4641s power stage (v inh ) and control bias (v inl ) input pins are brought out separately to allow freedom for implementing more sophisticated system configura- tions, such as: fully utilizing ltm4641s advanced output overvoltage (oov) protection features to protect the load (e.g., front page schematic or figure 46); providing rudi - mentary input surge ride-through protection (figure?47); performing dc/dc down conversion from a power rail below ltm4641s inherent uvlo thresholds (from a 3.3v bus in figure 49). if v inh and v inl are powered from separate rails, it is recommended to power up v inl prior to or concurrently with v inh . v inl should have a final value of at minimum 3.5v within 2ms of v inh exceeding 3.5v. the recommen - dation to sequence v inl ahead of or closely with v inh is not related at all to module device reliability but stems rather from a desire to assure that the control section of ltm4641 drives the mosfets in ltm4641s power stage deterministically whenever any appreciable v inh voltage is present. it is always permissible for v inl voltage to be presentregardless of the state of v inh however, realize that there is no uvlo detection on v inh . to prevent the control section from trying to regulate through a dropout condition or commencing switching activity in the absence of v inh potential, it is recommended
ltm4641 18 4641f applications informationpower supply features to implement a custom uvlo falling setting above the dropout curve in figure 4 (see also figure 11). lt3010-5 is shown in figure 47 to provide bias for v inl , to enable ride-through of 80v transients on v in . uvlo detection of v in is realized in this example by d2 creating a discharge path for v inl in the event of loss of v in . v inh and v inl have no specific power-down sequencing requirement, only that v inl should stay above 3.5v when - ever v inh is above 3.5v. v inl and v inh sequencing is inherently addressed by the ltm4641 in the figure 45 and figure 46 circuits. the v in and v inl start-up and shutdown waveforms of the figure 47 circuitbut with 1 output load and tmr tied to intv cc are shown in figure 2. the effect of the timing capacitor, c tmr , that normally generates a power-on reset (por) delay at start-up is negated by tying tmr to intv cc . the ~3ms v in -to-v out start-up delay time seen in figure 2 is due to por of the ltm4641s fault-monitoring circuitry and soft-start ramp (c ss ). scheme. during a load transient step-up, the control loop will command a higher inductor trough current to compensate for a deficiency in output voltage; the effective switching frequency will increase until the output voltage returns to normal (an overcurrent event, notwithstanding). during a load transient step-down, the control loop will command a lower inductor trough current to compensate for an excess of output voltage; the effective switching frequency will decrease until the output voltage returns to normal. the control loop perceives inductor current-sense information via the voltage signal that appears across the synchronous power mosfet, m bot , when m bot is on (this is commonly referred to in the industry as r ds(on) current sensing). the on-time of the one-shot timerand hence the power control mosfet, m top ,is given, in units of seconds, by: t on = 0.7v ? 10pf i ion (1) where i ion is in units of amperes. for output voltages greater than 3v, and for non-rail-tracking applications, no external r fset resistor is needed, and the i ion current (units: amperes) is set solely by the v inl voltage (units: volts) and the internal 1.3m v inl -to-f set resistor: i ion = v inl 1.3m (2) the switching frequency of operation of the ltm4641s buck converter power stage at full load in this scenario is given, in hz, by: f sw = v out 0.7v ? 1.3m ? 10pf (3) where v out is the desired nominal output voltage, in units of volts. an external r fset resistor can be applied when setting v out greater than 3v, if desired, to obtain increased switching frequency. usually, increasing switching frequency comes from a desire to reduce output voltage ripple and/or output capacitance requirementbut at a moderate penalty to dc/dc conversion efficiency. there are some limitations to how low an r fset value can be applied in practice due figure 2. start-up and shutdown waveforms of figure 47 circuit. tmr tied to intv cc to highlight v in and v inl sequencing without por delay. 1 load 2ms/div 4641 f02 v out 500mv/div v inl 5v/div v in 5v/div switching frequency (on time) selection and voltage dropout criteria (achievable v in -to-v out step-down ratios) the ltm4641 controller employs a current mode constant on-time architecture, in which the comp voltage corre - sponds to the trough inductor current at which the internal high side power mosfet (m top ) is commanded on by the control loopfor a duration of time proportional to controllers i on pin current (refer to figure 1). regulation is maintained by a pulsed frequency modulation (pfm)
ltm4641 19 4641f applications informationpower supply features to non-zero minimum off-time, dropout voltage, and maximum achievable switching frequency of operation. when an r fset resistor external to the ltm4641 is con - nected between v inl and f set to decrease the default on-time setting, the total i on current (units: amperes) is given by: i ion = v inl 1.3m + v inl r fset = v inl 1.3m ||r fset (4) where v inl is in units of volts and r fset is in units of ohms. r fset is needed for output voltage settings less than or equal to 3v out , and for rail-tracking applications. the minimum on-time the ltm4641 supports is 43ns, typi - cal, but guard banded conservatively to 75ns, maximum. therefore, for a conservative design, t on should be larger than 75ns, typical. from equation 1, it follows that i ion should be designed to be less than 93.3a. when an external r fset resistor is applied between v inl and r fset (and v inl and v inh are operating from the same railfigure 45 and figure 46), the switching frequency of operation of the power stage at full load, in hz, is given by: f sw = v out 0.7v ? 1.3m ||r fset ( ) ? 10pf (5) where r fset is in ohms, and v out is the desired nominal output voltage, in units of volts. in the general case, the switching frequency of the buck converter power stage at full load is given, in hz, by: f sw = v out v inh ? t on = v out ? i ion v inh ? 0.7v ? 10pf (6) see appendix c for a detailed discussion on the following topics: t 8iz tipvme uif txjudijoh dpouspmmfs cf pqfsbufe bu b higher switching frequency (i.e., programmed for a shorter on-time with r fset ) than that yielded by the internal 1.3m v inl -to-f set resistor alone for nominal output voltages of 3v and less? in rail-tracking applications? t 8ifo 7 inl and v inh are operated from separate supplies why should r fset ordinarily connect to the v in power source rather than v inh (figure 49)? when is it okay for r fset to connect to v inh (figure 47)? for application circuits of the form found in figure 45, figure 46, figure 47 and figure 51: see figure 3 for the maximum recommended value of r fset as a function of nominal target output voltage, and resulting full-load switching frequency corresponding to those r fset values. figure 3 can also be interpreted to provide the lowest recommended switching frequency for a given target output voltage. table 1 summarizes nominal values of r fset endorsed for some popular output voltages; use of commonly available 5% tolerance resistors or better with 100ppm/c temperature coefficient or better is recommended. figure 3. maximum recommended r fset (nominal values) for non-tracking applications, and resulting full-load operating switching frequency vs nominal output voltage nominal output voltage (v) 0 0.5 1 1.5 maximum recommended r fset value (m) typical f sw at full load (khz) 1 5 10 50 100 2 2.5 3 3.5 4 4.5 5 5.5 6 4641 f03 0.1 0.5 500 600 700 0 200 300 100 400 r fset vs v out region to avoid r fset not needed for v out > 3v max recommended r fset switching frequency
ltm4641 20 4641f applications informationpower supply features table 1. endorsed r fset resistor value vs output voltage for non-tracking applicationsand resulting full-load switching frequency (cf. figure 45, figure 46, figure 47, and figure 51 circuits) v out(nom) (v) r fset (m) (nearest eia-standard values) f sw (khz) 0.6 0.787 175 0.7 0.825 200 0.8 0.887 215 0.9 0.931 235 1.0 1.00 255 1.2 1.13 285 1.5 1.43 315 1.8 2.00 325 2.0 2.55 330 2.5 5.76 335 greater than 3.0 (not used) see figure 2 3.3 (not used) 360 5.0 (not used) 550 6.0 (not used) 660 in rail-tracking applications, it is recommended to use the r fset value corresponding to the lowest voltage needed to be regulated during output voltage ramp down. for example: to ramp v out down to 0.5v requires r fset to be not more than 750k (nominal) per figure 3. it is often permissible to use lower r fset values than those indicated in figure 3 and table 1 if, for example, lower output ripple voltage and/or a lower output capacitance is desired. however, be aware of three guiding principles: i. minimum on-time. ensure i ion < 93.3a. see equa - tions?1 and 4. ii. minimum off-time and dropout operation. the mini - mum off-time, t off(min) , is the shortest time required for the ltm4641 to perform the following tasks: turn on its power synchronous mosfet (m bot ), trip the control loops current comparator, and turn off m bot . the minimum input voltage on v inh , in volts, that one can regulate the output at and still avoid dropout is given by: v in(dropout) = v out ? 1 + t off(min) t on ? ? ? ? ? ? + r ps ? i out (7) where: t 7 out is nominal output voltage in volts. t u off(min) is the minimum length of time m bot can be on, after m top turns off. for a conservative de - sign, use a value of 300ns, taken from the electrical characteristics table. t u on is the on-time of the power control mosfet, m top , as programmed by the current flowing into the i on pin of ltm4641s internal control ic. t 3 ps is the series resistance of the modules power stage, from v inh to v out . for v in 6v, this is less than 50m, even at extreme temperatures (t j 125c). for v in < 6v, the effective series resistance increases due to drop in intv cc voltage and cor - responding decreased gate-drive enhancement of m top . printed circuit board (pcb) and/or cable resistance present in the copper planes and/or wires that physically connect the output of the module to the load adds to r ps s effective value. t * out is the load current on v out in amperes. for applications of the form shown in figure 45, fig- ure?46 and figure 47: the minimum allowable v inh voltage of operation to avoid dropout for 3v < v out 6v is shown in figure 4. the curves are a result of realizing that v in(dropout) equals v inh (neglecting msp voltage drop) when dropout actually occurs, and that equations 1 and 2 yield an expression for t on as a function of v inh . m top will be less fully enhanced during its on-time if drv cc is less than its nominal value of 5.3v (for example, when v inl < 6v and when drv cc bias is provided by intv cc ). drv cc s effect on r ps at low line is illustrated in figure 4. iii. maximum attainable f sw . the maximum attainable switching frequency of operation (in units of hz) for a given on-time (t on , in seconds) is governed simply by: f max = 1 t on + t off(min) (8) where a conservative value of 300ns can be used for t off(min) .
ltm4641 21 4641f applications informationpower supply features figure 4. line dropout voltage vs output voltage at no load and full load. figure 45, figure 46 and figure 47 circuit applications. r fset = open and r set1a , r set1b , r set2 values setting v out for regulation at or above 3v given that the pfm control scheme increases switching frequency (to as high as f max ) to maintain regulation during a transient load step-up, the design guidance is: set the steady-state operating frequency f sw to be less than f max . furthermore, when the ltm4641 is in dropout operation, the switching frequency of the converter is f max . it is best to avoid operation in dropout scenarios, because the control loop will rail comp high to command m top at highest possible duty cycle. if input voltage snaps upwards at a sufficiently high slew rate when comp has railed, the control loop may be unable provide satisfactory line rejection. see figure 11 to set the uvlo falling response of ltm4641 above the computed v in(dropout) voltage; this will inhibit switching action for v in < v in(dropout) . input voltage ripple, and any line sag between the input source supply and the v inh pinsand voltage drop across the power interrupt mosfet, msp, if usedmust be taken into ac - count by the system designer. setting the output voltage; the differential remote sense amplifier a built-in differential remote-sense amplifier enables preci - sion regulation at the point-of-load (pol), compensating for any voltage drops in the systems output distribution path: the total variation of ltm4641s output dc voltage over line, load, and temperature is better than 1.5%. the basic feedback connection between the pol and the modules feedback sense pins is shown in figure 5. figure 5. basic feedback remote sense connections and techniques; setting the output voltage + ? + 8.2k v osns + v osns ? v orb + v orb ? sgnd ict test point v out c out(bulk) c out(mlcc) r set2 r set1a c ffb c ffa ict test point sgnd connects to gnd internal to module. keep module sgnd routes/planes separate from gnd on motherboard 4641 f05 place all feedback components local to the ltm4641 v fb to error amplifier 8.2k 8.2k 8.2k ltm4641 true differential remote sense amplifier gnd v out r set1b route feedback signal as a differential pair (or twisted pair if using wires). sandwich between ground planes to form a protective shield guarding against stray noise load c ffa , c ffb : feedforward capacitors yeild improved transient response when filtering v out with only mlcc output capacitors (c out(mlcc) ) output voltage setting (v) 3 line dropout voltage (v) 6.0 7.0 8.0 5 4641 f04 5.0 4.0 5.5 6.5 7.5 4.5 3.5 3.0 3.5 4 4.5 5.5 6 10a output, drv cc biased from intv cc (5.3v nom ) 10a output, drv cc biased to 5.3v by external supply no load, drv cc 4.2v(uvlo rising) and 3.5v (uvlo falling)
ltm4641 22 4641f applications informationpower supply features the output voltage at the pol is differentially sensed via a symmetrical impedance-divider network. in figure 1 and figure 5, it is seen that the control loop regulates the output voltage such that the differential v osns + -to-v osns C feedback signal voltage is the lesser of the track/ss pin voltage or the regulators nominal bandgap voltage of 600mv. the arrangement and values of the resistors in the symmetrical impedance-divider network set the output voltage. the remote sense pins (v osns + , v osns C ) have redundant connections internal to the module to readback pins (v orb + , v orb C ). the readback pins provide a means to verify the integrity of the feedback signal connection during moth- erboard ict (in circuit test). the importance of verifying the integrity of the connection of the feedback signal to the output voltage prior to powering up the input voltage cannot be understated. if one or both feedback pins are left electrically floating due to manufacturing assembly defect, for example, or if the remote-sense pins are short circuited to each other, the control loop and overvoltage- detector circuitry have no awareness of the actual output voltage condition. a compromised feedback connection presents a very real danger of (1) the control loop com - manding on m top at the highest possible duty cycledue to the lack of negative feedbackand (2) the ltm4641s protection circuitry being unaware of any issue. in a pro - duction environment, modern day ict can easily catch any such stuffing or assembly errors; in a lab or prototyping environment, an ohmmeter can do the job. for many applications that use a mixture of mlcc and bulk (low esr tantalum or polymer) output capacitors, the symmetrical impedance-divider network that feeds back the pols voltage to the module need only be constructed with resistors r set1a and r set1b , for output voltages of 1.2v out and lower. r set2 must be present for output voltages in excess of 1.2v out . r set1a and r set1b should always have the same nominal value. applications with mlcc-only output capacitors (see output capacitors and loop stability in following pages) will demonstrate improved transient response when feedforward capaci - tors c ffa and c ffb , nominally equal in value, are installed electrically in parallel with r set1a and r set1b , respectively. use of 0.1% tolerance resistors (or better) for r set1a , r set1b , and r set2 are recommendedwith temperature coefficients of resistance suitable for ones operating range of pcb temperatureto assure that output voltage error introduced by resistor value variation is acceptable for the application. smt resistors with t.c.r.s of 25ppm/c and better are readily available in the marketplace. for output voltage settings less than or equal to 1.2v out , r set2 is not needed, and r set1a and r set1b are given by: r set1a = r set1b = v out 0.6v ? 1 ? ? ? ? ? ? ? 8.2k (9) for output voltages above 1.2v out , r set1a (and r set1b ) should be set equal to 8.2k (or less, if 8.2k is not a convenient value for the user), and rset2 is then given by: r set2 = 2 ? r set1a v out 0.6 ? r set1a 8.2k ? 1 (10) it is always permissible to select a value for r set1a (and r set1b ) less than that given by equation 9and then calculate a valid value for r set2 from equation 10as long as r set1a and r set1b are designed to withstand the higher resulting power dissipation. when v out is in regulation, the voltages at v osns + and v osns C are given by: v vosns + = 0.6v 8.2k ||r set1a ||r set2 ( ) + ? v gnd r set1a ? ? ? ? ? ? ? r set1a ||16.4k ( ) (11) and v vosns C = v vosns + C 0.6v (12) respectively. ?v gnd is the voltage drop between ground at the pol and ltm4641s sgnd pins in volts. this voltage espq jt vtvbmmz foujsfmz b sftvmu pg * t 3 espq jo uif pvuqvu distribution pathlargest when maximum load current is being drawn: ?v gnd = v gnd(pol) C v sgnd(ltm4641) (13)
ltm4641 23 4641f applications informationpower supply features with r set1a , r set1b , and r set2 determined, double-check the output voltage setting with: v out = 0.6v ? 1 + r set1a 8.2k + 2 ? r set1a r set2 ? ? ? ? ? ? (14) some recommended values for r set1a , r set1b , and r set2 for popular output voltages are shown in table 2. table 2. recommended r set1a , r set1b and r set2 values for some popular output voltages, cf. figure 5 feedback connections. v out r set1a , r set1b r set2 0.6v 0 (not used) 0.7v 1.37k (not used) 0.8v 2.74k (not used) 0.9v 4.12k (not used) 1.0v 5.49k (not used) 1.2v 8.2k (not used) 1.5v 8.2k 33.2k 1.8v 8.2k 16.5k 2.0v 8.2k 12.4k 2.5v 8.2k 7.5k 3.3v 8.2k 4.7k 5.0v 8.2k 2.61k 6.0v 8.2k 2.05k see appendix d for a detailed discussion on the following topics: t 8ibu jt uif sbujpobmf gps vtjoh b tznnfusjdbm sftjtups network? t 8ibu tipvme * ep jg * dboopu tijfme uif ejggfsfoujbm tfotf feedback lines with gnd? (i anticipate differential mode noise in the feedback signal?) t 8ibu tipvme * ep jg uif npevmf boe uif mpbet bsf separated by a significant distance (~50cm or more), or if the load current flows through a cable assembly or power connector? (i anticipate common mode noise in the feedback signal?) input capacitors the ltm4641 module should be connected to a low ac impedance, nominally dc output voltage source. mlcc input bypass capacitors must be provided externally, as close in proximity to the module as possible (see figure?43). if external mosfet msp is not used (figure 45), two 10f or four 4.7f ceramic capacitors should be electrically connected directly between the v inh and gnd pins. if msp is used (figure?46, figure?47 and figure 49), then msp must be placed as close to the ltm4641s v inh pins as possible, and two 10f or four 4.7f ceramic capaci - tors should be electrically connected directly between the drain of msp and gnd (see figure 44). a 47f to 100f surface mount bulk capacitor can be used to supplement input power bypassing, and can share the burden of any local ceramic capacitors in filtering the power stages ripple current. if low impedance power planes are used to bring v in to the vicinity of the module, input source impedance will be low enough that bulk capacitors will not be needed. a localized bulk input capacitor is needed when an underdamped lc-resonant tank is formed by routing long input leads or traces (low esr inductance) bypassed only with mlccs (ultralow esr capacitance). neglecting the inductor peak-to-peak current ripple, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) ? d ? 1?d ( ) (15) where is the power conversion efficiency of the ltm4641 module and d is the duty cycle on-time of m top . the bulk capacitor can be a switcher-rated electrolytic aluminum capacitor or a polymer capacitor. for a buck converter, the switching duty cycle of m top can be estimated as: d = v out v in (16) output capacitors and loop stability/loop compensation the current mode constant on-time architecture enables very high step-down input-to-output ratios with compel - ling transient response. it also enables cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. the ltm4641 is internally compensated to yield stability over all operating conditions.
ltm4641 24 4641f applications informationpower supply features the output capacitors c out(bulk) and c out(mlcc) must be chosen with low enough effective series resistance (esr) to meet the output voltage ripple requirements and provide localized bypassing for the load. although the ltm4641 provides fast transient response, the output voltage at the pol is reliant on nearby charge stored in a reservoir of ceramic capacitors c out(mlcc) to minimize sag and overshoot in the initial microseconds of a high di/dt transient load step-up and step-down, respectively. if used, c out(bulk) can be comprised of low esr tantalum or low esr polymer capacitor(s); these capacitors then serve as a local reservoir to replenish the mlccs during transient load events. it is also possible to use c out(mlcc) only, however, the use of feedforward capacitors, c ff , should then be installed in the remote-sense feedback path, to obtain an optimized transient response (see figure?5 feedback connections). the c out(mlcc) ceramic capacitors should be at least x5r-type material. x5r-type and x7r-type mlccs are recommended when operating pcb temperatures are not more than 85c and 125c, respectively. both materials are renown in the industry for having a relatively low ca - pacitance change over their respective temperature range of operation (15%). however, x5r and x7r mlccs do exhibit significant loss of capacitance with applied dc voltage and are subject to aging effects, and this must be taken into account in any system design. refer to the capacitor manufacturers specifications for details. the typical output capacitance range is between 200f to 800f. the system designer should use discretion in determining whether additional output filtering may be needed, if further reduction of output rippleor output voltage deviation during dynamic load or line transient eventsis required. in table 9, guidelines are provided for output capacitor selection, for various operating conditions. the table optimizes total equivalent esr and total bulk capacitance for the transient load step performance. stability criteria is considered. the linear technology ltpowercad? de - sign tool is available for transient simulation and stability analysis, if desired. pulse-skipping mode vs forced continuous mode in applications where high dc/dc conversion efficiency at light-load currents is highly desiredwhen the input voltage source is a battery, for examplepulse-skipping mode operation should be employed. pulse-skipping mode operation prevents power flow from the output capacitors to the input source. be aware, however, due to m bot s re - sulting asynchronous operation at light load, applications employing pulse-skipping mode may necessitate more output capacitance and/or a higher ov pgm setting than operation in forced continuous mode would. pulse-skipping mode is activated by connecting fcb to intv cc . forced continuous operation is activated by con - necting fcb to sgnd. be aware that in pulse-skipping mode and ultralight loads (say, less than 20ma out), the v ing voltage may appear as a sawtooth waveform as a result of being charge-pumped at a slower rate, to conserve energy. see appendix e for more information on how pulse-skipping mode works. soft-start, rail-tracking and start-up into pre-bias the track/ss pin can be used to either soft-start the output of the ltm4641 regulator, or make ltm4641s output voltage track another rail coincidentally or ratio - metrically. when run or hyst is low, the track/ss pin is discharged. when run and hyst are released, track/ss sources a microamp of current. when a soft-start capacitor, c ss , is applied to the pin, the current source is responsible for generating an output volt - age turn-on time of 0.6ms per nanofarad of capacitance. the power stage is high impedance (m top and m bot are off) until the track/ss pin voltage exceeds v fb , the remote-sense differential amplifiers output voltage. this allows power-up into pre-biased output voltage conditions without sinking of current from the output capacitors. when track/ss exceeds the control ics 600mv bandgap voltage, v fb is regulated at 600mv and v out reaches its nominal output voltage.
ltm4641 25 4641f applications informationpower supply features figure 6 shows idealized output voltage waveforms for applications in which ltm4641s output (v out ) tracks a master rail (v master ) coincidently and ratiometrically, respectively. (3) choose output capacitors and input capacitors for the design in the same manner as is done for nontracking applications. to fulfill a coincident rail-tracking requirement, recognize that when the output voltage of the master rail reaches the tracking rails nominal fs voltage, the track/ss pin of the ltm4641 (tracking slave) needs to be 600mv. this can be satisfied by forming a resistor-divider network composed of r tac and r tbc , interfacing v out_master to track/ss of the ltm4641 tracking slave, and terminating to sgnd of the ltm4641 tracking slave. in figure 7 and figure 8, u1 generates a master rail while u2 generates a coincident-tracking rail that follows u1s output. values of r tac and r tbc are selected such that: r tac = v out_slave_c (fs output) 0.6v ? 1 ? ? ? ? ? ? ? r tbc (17) in the example circuit of figure 7, the master rail generated by u1 ramps up its output to 1.8v. the coincident-tracking rail is generated by u2 and has a nominal fs output voltage of 1v. values of r tac and r tbc are determined such that when u1s output reaches 1v, the track/ss pin of u2 reaches ~600mv; choosing r tbc to be 10k yields r tac 7f7 o t l ps _ffl *u jt common to choose resistor values of 10k or less for this task, so that voltage offset errors introduced by the 1a current source on track/ss working into the r tac /r tbc network are sufficiently small. to fulfill a ratiometric rail-tracking requirement, recognize that when the output voltage of the master rail reaches its final fs value, the track/ss pin of the ltm4641 (tracking slave) needs to reach 600mv. this can be satis - fied by forming a resistor-divider network composed of r tar and r tbr , interfacing v out_master to track/ss of the ltm4641 tracking slave, and terminating to sgnd of the ltm4641 tracking slave. in figure 7 and figure 8, u3 generates a ratiometric-tracking rail that follows u1s output. values of r tar and r tbr are selected such that: r tar = v out_master (fs_output) 0.6v ? 1 ? ? ? ? ? ? ? r tbr (18) time v master v out output voltage 4641 f06a time v master v out output voltage 4641 f06b (6a) coincident tracking (6b) ratiometric tracking figure 6. two different modes of output voltage tracking to configure ltm4641 for coincident or ratiometric tracking, begin the design (initially) the same way as for nontracking applications: (1) determine the r set1a , r set1b , and r set2 values ap - propriate for the final, full-scale (fs) output voltage. (2) determine the r fset resistor needed to guarantee ramp down of the output voltage to the desired value. for example, if it is necessary for v out to ramp down to 0.8v while tracking the master rail, then r fset is recommended from table 1 to be ~887k. if ramp- down tracking is not needed, then r fset can be chosen according to table 1 (or figure 3) and the fs output voltage of the ltm4641 generated rail.
ltm4641 26 4641f applications informationpower supply features figure 7. examples of ltm4641 performing coincident and ratiometric rail-tracking. cf. figure 8 waveforms + r setm2 16.4k r setr2 33.2k 4641 f07 r mfset 2m u1 v out ramp time t softstart = 0.6ms/nf ? c ss (c ss in nf) c outm(mlcc) 100f 6.3v 3 c inm(mlcc) 10f 50v 2 c inm(bulk) 50v v in 4v to 38v (4.5v start-up) v out_master 1.8v up to 10a local high frequency decoupling r setm1a 8.2k r setm1b 8.2k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run run run v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr c ss 4.7nf track/ss v ing v ingp sw v inh u1 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 1 1 1 1 1 + r cfset 680k r tac 6.65k r tbc 10k c outsc(mlcc) 100f 6.3v 4 c insc(mlcc) 10f 50v 2 c insc(bulk) 50v v out_slave_c 1v up to 10a local high frequency decoupling r setc1a 5.49k r setc1b 5.49k coincedent tracking of the 1.8v rail load v osns + v out v inl f set intv cc drv cc iovretry ovlo run v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u2 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 2 2 2 v out_master 2 2 run r rfset 1m r tar 20k r tbr 10k c outsr(mlcc) 100f 6.3v 4 c insr(mlcc) 10f 50v 2 v out_slave_r 1.5v up to 10a local high frequency decoupling r setr1a 8.2k c ffra 220pf c ffrb 220pf c ffma 220pf c ffmb 220pf r setr1b 8.2k ratiometric tracking of the 1.8v rail load v osns + v out v inl f set intv cc drv cc iovretry ovlo run 1 , u1, u2 and u3 sgnd ( ) connect to gnd internal to their respective modules. keep sgnd routes/planes of modules separate from each other and from gnd on motherboard v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u3 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 3 2 , 3 3 3 v out_master 3 3 + c insr(bulk) 50v sw sw
ltm4641 27 4641f applications informationpower supply features in the example circuit of figure 7, the master rail generated by u1 ramps up its output to 1.8v. the ratiometric-tracking rail is generated by u3 and has a nominal fs output volt - age of 1.5v. values of r tar and r tbr are determined such that when u1s output reaches its final value, 1.8v, the track/ss pin of u3 reaches ~600mv: choosing r tbr to be 10k yields r tar = (1.8v/0.6v C 1) ? 10k, or ~20k. it is common to choose resistor values of 10k or less for this task, so that errors introduced by the 1a current source on track/ss are sufficiently small. figure 8 shows an oscilloscope snapshot of the output voltage waveforms of the modules configured per the figure 7 circuit, with 6 load on v out_master and no load on the v out_slave_c and v out_slave_r outputs. figure 8. output voltage waveforms of u1, u2 and u3. cf. figure 7 circuit. pin to the mosfet driver circuitry. in most cases, connect intv cc to drv cc . the intv cc regulator can source up to 30ma, continuous, which is sufficient for powering drv cc , even at the ltm4641s highest recommended switching frequency (6v out condition). the power loss in the ldo can be considerable at high input voltage, given by: p loss(intvcc_ldo) = (v inl C 5.3v) ? (5ma + i drvcc ) (19) this power loss can be virtually eliminated when a ~5v to 6v rail is available to overdrive the intv cc /drv cc pins through a schottky diode, as shown in the figure 51 circuit. this is because the ldo can only pull intv cc s voltage in an upward directionthat is to say, the series-pass element turns off when intv cc exceeds the ldo control loops regulation setpoint. infrared thermal images in figures 52 to 55 illustrate operating conditions in which up to ~5c reduction in package surface temperature is obtained by employing this technique. note the importance to provide a diode-ored path from v in to v inl and from intv cc /drv cc to v inl when intv cc /drv cc is overdriven by an auxiliary rail (or v out ). this assures proper mosfet driver behavior regardless of disappearance/appearance of v inl versus v aux , in any combination or sequence of rail ramp-up/ramp-down events. the series-connected schottky diode internal to the ltm4641 that feeds the ldo from v inl assures proper mosfet driver and internal logic behavior, even in the event of rapid discharging and restoration of v inl . a housekeeping circuit that monitors drv cc voltage in - hibits switching action until drv cc exceeds 4.05v. once switching action commences, drv cc is allowed to fall to 3.35v before switching action is inhibited. the drv cc voltage monitor has glitch immunity characteristics as shown in figure 12. drv cc current is proportional to switching frequency. for applications with extremely fast output voltage start-up (e.g., c ss < 100pf on track/ss, or rail tracking very fast rails with sub 60s turn-on time), switching frequency may u1 v out 1v/div u2 v out 1v/div u3 v out 1v/div run 5v/div 2ms/div 4641 f08 for applications that do not require tracking or sequencing, applying at least 100pf on the track/ss pin is recom- mended, corresponding to ~60s output voltage start-up ramp time. the resulting soft-start period will limit start-up input surge current and output voltage overshoot. intv cc and drv cc the ltm4641 module has an internal 5.3v low dropout regulator whose input is fed from the low current input voltage bias pin, v inl , through a schottky diode. the out - put, intv cc , is used to power control and housekeeping circuitry and the mosfet drivers, and is up-and-running whenever bias on v inl is present. drv cc is the power input
ltm4641 28 4641f applications informationpower supply features conceivably approach f max at start-up, however briefly (see equation 8). when biasing drv cc from intv cc in such applications, intv cc may require additional bypass capacitance to ride through the resulting current surge on drv cc . intv cc can by bypassed with up to 4.7f (20% tolerance) of external decoupling capacitance. 1v ref a housekeeping ic internal to the ltm4641 generates a 1v 1.5% reference voltage. this voltage reference is generated independent of the control ics 600mv bandgap voltage. the 1v ref should only be used to alter the ov pgm threshold programming voltage for the fast oov compara - tor (see fast output overvoltage comparator threshold section) or to implement an auxiliary overtemperature detector with an ntc having ultrahigh resistance (470k at 25c, b-value < 5000k)in the manner shown in figure?47. loading 1v ref beyond 100a is not recommended. 1v ref must become established quickly at start-up to properly bias ov pgm , and therefore no external capacitance should be applied to this pin. to minimize disturbance to the ov pgm voltage, dynamic step-loading of the 1v ref is not recommended. figure 9 shows the step response of 1v ref to a 0a to 100a step load with 100a/s slew rates, and the resulting impact to ov pgm s voltage waveform. temp, otbh and overtemperature protection as seen in figure 1, a resistor-ntc-divider network formed between 1v ref and sgnd generates temp, an analog temperature indicator pin. the pin nominally measures ~0.98v at 25c and colder, and ~585mv at 125c. a graph of the relationship between junction temperature, ntc resistance, and temp voltage is found in figure 10. the temp pin also connects indirectly to a comparator input whose output can pull hyst low to inhibit switch - ing action. if temp falls below 438mv, corresponding to a junction temperature of ~147c, switching action is inhibited. if otbh is logic low when temp falls below 438mv, a latchoff overtemperature event is registered. restarting regulation after a latchoff event has occurred is explained in detail in the start-up/shutdown section. if otbh is open circuit when temp falls below 438mv, a nonlatching overtemperature event is registered: switch - ing action can resume when the units cools off and the temp pin rises above 514mv, corresponding to a junction temperature of ~136c. the ltm4641s overtemperature protection feature is in - tended to protect the device during momentary overload conditions. recognize that the ltm4641 is rated for 125c junction, absolute maximum, and that junction temperature exceeds 125c when overtemperature protection is active. continuous operation above the specified maximum op - erating junction temperature may impair device reliability. the overtemperature protection circuit can be disabled by connecting temp to 1v ref . with moderate linear cir - cuit analysis, the information in figure 10 and figure 62 (appendix a) can be used to alter the overtemperature inception and recovery thresholds. if desired, the thresh - olds can be increased by applying a resistor from temp to 1v ref , or decreased by applying a resistor from temp to sgnd. the overtemperature comparator contains built-in filtering, yielding glitch immunity characteristics shown in figure 12. 20s/div 4641 f09 ov pgm 10mv/div ac-coupled i 1vref 50a/div 1v ref 100mv/div ac-coupled figure 9. response of 1v ref to 0a ? 100a load steps applied at 100a/sand resulting disturbance and recovery of ov pgm . figure 43 circuit. do not load 1v ref arbitrarily
ltm4641 29 4641f applications informationinput protection features input monitoring pins: uvlo, iovretry, ovlo the uvlo pin feeds directly into the inverting input of a comparator whose trip threshold is 0.5v. the behavior of the uvlo pin is an example of a nonlatching fault: when the uvlo pin falls below 0.5v, hyst is pulled low and switching action is inhibited; when the uvlo pin exceeds 0.5v, hyst goes logic high and switching action can resume. the iovretry and ovlo pins each feed directly into noninverting inputs of comparators whose trip thresholds are 0.5v. the behavior of the iovretry pin is also an example of a nonlatching fault pin: when the iovretry pin exceeds 0.5v, hyst is pulled low and switching action is inhibited; when iovretry falls below 0.5v, switching action can resume. the behavior of the ovlo pin is an example of a latchoff fault pin: when the ovlo pin exceeds 0.5v, hyst is pulled low and switching action is inhibited; when ovlo subsequently falls below 0.5v, hyst remains latched low, and switching action cannot occur until the latch has been reset. restarting regulation after a latchoff event has occurred is explained in detail in the start-up/shutdown section. these three pins give added flexibility to tailor some be - haviors of the ltm4641. the uvlo pin input is primarily used to set customized uvlo rising and uvlo falling thresholds, utilizing a high impedance connection to the hyst pin to obtain hysteresis. there are times when the ltm4641s default uvlo rising and uvlo falling thresholds of 4.5v in rising (maximum) and 4v in falling (maximum) are not suitable. for example, it can be convenient to ap - ply customized uvlo settings to inhibit switching prior to entering a region of possible dropout operation (figure 51). it may be desirable to set a very large uvlo hysteresis, if line sag is problematic. uvlo is highly recommended to be customized to monitor the source supply feeding v inh when v inl is biased from an auxiliary rail (figure 49). the uvlo pin input may also be used to provide novel circuit solutions such as one found in figure 47: to detect an overtemperature event in mspsensed via an external ntc in close proximity to the power interrupt mosfet, msp; and to respond to msp overtemperature by inhibiting switching action and turning off msp until the mosfet returns to normal temperatures. iovretry is primarily used to set the input voltage (v in ) threshold above which switching action is inhibited, but not latch off. ovlo is primarily used to set the input volt - age (v in ) threshold above which switching action latches off. just as the uvlo pin can be used in versatile ways, so can iovretry and ovlo. consult appendix a to see the uvlo/iovretry/ovlo pins functions in greater detail. the most common arrangement of components connect - ing v in to uvlo, hyst, iovretry and ovlo is shown in figure 11. junction temperature (c) ?55 ntc resistance () temp pin voltage (v) 10000 100000 1000000 ?15 25 65 105 145 185 4641 f10 1000 0.75 0.25 0.35 0.45 0.55 0.65 0.85 0.95 figure 10. relationship of ntc resistance to junction temperature and resulting temp voltage. curves for nominal values and calculated extreme values shown figure 11. setting the ltm4641 custom uvlo rising and uvlo falling thresholds, nonlatching input overvoltage threshold, and latching input overvoltage threshold + v inl v inh ltm4641 uvlo uvlo < 0.5v = off hyst pulls up when on, hyst pulls down when off hyst iovretry iovretry > 0.5v = off ovlo > 0.5v = latchoff ovlo sgnd gnd 4641 f11 r tuv c in(mlcc) 10f 2 c in(bulk) v in r buv r tov r mov r bov r hyst sgnd connects to gnd internal to module. keep sgnd routes/planes separate from gnd on motherboard
ltm4641 30 4641f applications informationinput protection features variables to define up-front are as follows: ? v su : v in start-up voltage, in volts. this is the custom - ized uvlo rising voltage. ? v sd : v in shutdown voltage, in volts. this is the custom - ized uvlo falling voltage. ? v hyst : the value of the voltage on the hyst pin (in volts) when switching action is on and just prior to the input voltage (v in ) falling below v sd . ? r hyst : the hysteresis-setting resistor. if used, r hyst is recommended to take on a value of 1m or higher, so that the hyst voltage is negligibly affected by external loading. ? v ov : the input voltage above which a latchoff input overvoltage event occurs. ? v rt : the input voltage above which a nonlatching input overvoltage event occurs. then, r tuv and r buv are given by: r tuv = v su ? v sd v hyst s r hyst (20) and r buv = uvov th v su ? uvov th r tuv ? uvov th r hyst (21) uvov th is nominally 0.5v, from the electrical characteris - tics table. the value of v hyst used in the above equations requires more careful consideration. review figure?1 and assess system details of the specific application in which the ltm4641 is being placed. it is known from the electri - cal characteristics table that when v inl 6v that intv cc = 5.3v; and we see the voltage on the hyst pin, when switching action is on, is v hyst(switching_on) , 5.1v nominally. observe that if the run pin were driven high by 3.3v logic, however, that v hyst would be a schottky diode forward-voltage drop above 3.3vand v hyst in that instance would be 3.6v. if v sd is targeted below 6v in , it is necessary to consider that v hyst s pull-up voltage, intv cc , is decreasing with v inl . for example, at v inl = 4.5v input, intv cc is nominally 4.3v (v intvcc(lowline) ), and it is inferred (in that scenario) that v hyst would be closer to 4.1v, when run is floating. it is the moderately weak pull-up strength of hyst (10k pull-up to intv cc ), and the desire for any loading of the hyst signal to negligibly alter the hyst logic-high output voltage level (less than ~50mv), that motivates a high impedance (~1m) hysteresis-setting resistor to interface between hyst and uvlo, when custom uvlo settings are desired. the customized uvlo start-up and shutdown input voltage settings can be double-checked with: v su = uvov th s r tuv r buv ||r hyst + 1 ? ? ? ? ? ? (22) v sd = v su ? v hyst r hyst s r tuv (23) to set the input overvoltage (latching and nonlatching) thresholds, choose first how much current, i div , to continu- ally have drawn by the r tov /r mov /r bov resistor-divider string for this function, at ultrahigh line. 10a to 20a is a normal amount to allocate. the total resistance of the divider string is then given by: r tot = v ov i div (24) then, the resistors in the input overvoltage divider are given by: r bov = r tot s uvov th v ov , (25) r mov = uvov th s r tot s 1 v rt ? 1 v ov ? ? ? ? ? ? , (26) r tov = r tot C r m C r b (27) it may be tempting to try rearranging these equations so that r tov s value is fixed, first, and to compute r mov and r bov subsequently. however, due to large divide- down ratio (usually) of ultrahigh line input voltage down to these pins with ~0.5v thresholds, the rounding off of r mov and r bov to nearest eia standard values after fixing
ltm4641 31 4641f applications informationinput protection features r tov s value in place often significantly alters one or both v in referred overvoltage thresholds. it is more efficient to work through equations 24 to 27 in the sequence shown and iterate (if necessary) towards finding convenient (eia standard) resistor values. the latchoff input overvoltage threshold can be double- checked with: v ov = uvov th ? r tov + r mov r bov + 1 ? ? ? ? ? ? (28) the nonlatching overvoltage threshold can be double- checked with: v rt = uvov th ? r tov r mov + r bov ( ) + 1 ? ? ? ? ? ? (29) the uvlo, iovretry and ovlo pins do not require any filter capacitance due to built-in filtering in the ltm4641s housekeeping ic. this results in glitch immunity with characteristics shown in figure 12. the ltm4641 powers up its output when the following conditions are met: t 36/ fydffet 7 opnjobm 7 pwfsufnqfsbuvsf power-on reset (por) and timeout delay times do not apply to run. t mm opombudijoh gbvmunpojups qjot ibwf cffo jo uifjs operationally valid states for the full duration of the por delay time, set optionally by c tmr (the capacitor on the tmr pin). explicit pins and operationally valid thresholds follow: a. drv cc > 4.05v. in the circuits of figures 45 and 46, this is guaranteed for v inl 4.5v, minimum. in figure?49, this requirement is met when the auxiliary bias supply exceeds 4.05v. b. uvlo > 500mv c. iovretry < 500mv d. temp > 514mv (when otbh is electrically open circuit) t /p mbudipgg gbvmu dpoejujpot bsf qsftfou boe uif -5.f is not in a latched off state from any previously detected latchoff fault condition. if a latchoff fault condition oc - curs/occurred, the ltm4641 must be unlatched by a logic high latch signal: if all latchoff fault-monitoring pins are in operationally valid states when latch transitions from logic low to high, the ltm4641 becomes immediately unlatched; if, instead, any latchoff fault-monitoring pin is outside its operationally valid state when latch is logic high, the ltm4641 becomes unlatched if latch remains logic high after all latchoff fault-monitoring pins have been in their operationally valid states for the full duration of the timeout delay time (set optionally by c tmr ). explicit pins and operationally valid thresholds follow: a. ovlo < 500mv b. temp > 514mv (when otbh is logic low) c. crowbar < 1.5v the por and timeout delay time is 9ms per nanofarad of c tmr capacitance. if c tmr is not used, the por and timeout delay time is ~90s. figure 12. transient duration vs comparator overdrive glitch immunity characteristics. monitored signals: uvlo, iovretry, ovlo, temp, crowbar and drv cc comparator overdrive past threshold (%) 0.1 400 typical transient duration (s) 500 600 700 1 10 100 4641 f12 300 200 100 0 respective fault condition becomes detected glitch ignored start-up/shutdown and run enable; power-on reset and timeout delay time the ltm4641 is a feature-rich and versatile self-contained dc/dc converter system, and includes multiple on-board supply monitors. the inputs to several monitors are avail - able to the user for system customization (uvlo, ovlo, iovretry and temp).
ltm4641 32 4641f applications informationload protection features if any nonlatching fault conditions occur, internal circuitry pulls hyst low and switching action is inhibited. the power stage will be high impedance until the aforementioned start- up conditions are met. if any latchoff fault condition occurs, hyst is latched low and switching action is inhibited until the ltm4641 is unlatched (by pulling latch logic high) or v inl power is recycled (with intv cc falling below 2v). the ltm4641 can be configured to restart autonomously after an adjustable timeout delay timeinstead of ex- hibiting latchoff behaviorby leaving latch logic high (connected to intv cc , for example) and setting the hiccup retry timeout delay time with c tmr (see figure 47). be reminded that use of c tmr also introduces por behavior, yet the por and timeout delay timers operate indepen - dently. the effect of c tmr can be negated by pulling the tmr pin to intv cc . switching action will be inhibited if any of the following occur: ? run is less than 1.15v (nominal; 0.8v, overtemperature). not a fault; no por or timeout delay time is imposed. ? any nonlatching faults occur: a. drv cc falls below 3.35v. in the figure 45 and figure 46 circuits, this happens at v inl < 4v, maximum. b. uvlo falls below 0.5v. c. iovretry exceeds 0.5v. d. temp falls below 438mv when otbh is electrically open circuit. ? any latchoff faults occur: a. ovlo exceeds 0.5v. b. crowbar exceeds 1.5v. c. temp falls below 438mv when otbh is logic low. the ltm4641s state diagram is provided in appendix?b . start-up and shutdown mechanisms for any given op - erating scenario are identified in the state diagram. the temp and drv cc pins have built-in hysteresis. the uvlo, iovretry, ovlo, temp, crowbar and drv cc pins con- nect to comparators with built-in glitch immunity, with characteristics indicated in figure 12. overcurrent foldback protection the ltm4641 has overcurrent protection (ocp). in a short circuit from v out to gnd, the internal current comparator threshold folds back during a short to reduce the output current, progressively down to about one-third of its normal value (down from 24a to 8a, typical). to recover from foldback current limit, the excessive load or low impedance short needs to be removed. foldback current limiting action is disabled during soft-start and tracking start-up. power good indicator and latching output overvoltage protection internal overvoltage and undervoltage comparators assert the open-drain pgood output logic low if the output voltage is outside 10% of nominal, after a 12s blanking time. the blanking time allows the output voltage to experience brief excursions (due to large load-step transients, for example) without nuisance-tripping pgood. the pgood output is deasserted without any deliberate blanking time when the output voltage returns to (or enters) the power good window, with ~2% to 3% of hysteresis. if the feed - back voltage exceeds the upper pgood valid limit, the synchronous power mosfet, m bot , turns on (with no blanking time)to try sinking current from the output to gnd, through ltm4641s power inductoruntil the output voltage returns to the pgood valid region. if the output voltage exceeds an adjustable threshold set by ov pgm , whose default value corresponds to 11% above nominal, the ltm4641 pulls its crowbar output logic high imme - diately (500ns response time, maximum) and latches off its output voltage: the power stage becomes high impedance, with both m top and m bot turning off and staying latched off; furthermore, msps gate is pulled to v inh potential rapidly (<2.6s response time, maximum), to disconnect the input source voltage from the modules power stage. restarting regulation after a latchoff event has occurred is explained in detail in the start-up/shutdown section. the behavior of turning on the synchronous mosfet dur - ing detection of an output overvoltage is a rudimentary and popular kind of output overvoltage protection scheme commonly found in the power supply and semiconductor control ic industry. it can provide mediocre overvoltage
ltm4641 33 4641f applications informationload protection features protection during severe load current step-down events, but is not very effective at protecting loads from genuine fault conditions such as a short circuited high side power switching mosfet. furthermore, such schemes tend to be implemented with the overvoltage detectors threshold dependent on the same bandgap voltage that the output is being regulated to. applications needing superior output overvoltage and load protection require the performance achieved with the output crowbar mosfet, mcb and power interrupt switch, msp, and ltm4641s use of an independent reference voltage(1v ref ) to generate an oov threshold. power-interrupt mosfet (msp), crowbar pin and output crowbar mosfet (mcb) within 500ns (maximum) of the control-loop-referred feedback signal, v fb , exceeding the voltage on ov pgm (plus-or-minus ovp err ), an oov event is detected, and the crowbar output swings high enough to turn on an optional crowbaring device (mcb) residing on v out . no more than 2.6s after oov detection, v ing is discharged and an optional power interrupt switch, msp, disconnects the ltm4641s power stage from the input source supply. when mcb and msp are used in conjunction as shown in the figure 46 circuit, the ltm4641 is able to provide best- in-class output overvoltage protection against arguably the most despised failure mode high step-down buck convert - ers can theoretically suffer: an electrical short between the input source to the output, via the switching node. turning on mcb upon detection of oov helps discharge the output capacitors and prevent any further positive ex - cursion of output voltage by transforming residual energy in ltm4641s power stage into heat; meanwhile, turning off msp removes a path for current flow between the in - put power source and the outputpreventing hazardous (input) voltage from reaching the precious load. it should be noted that when an oov event is detected, crowbar is not held high (equivalently, mcb is not left turned on) indefinitely. the act of pulling crowbar high (above 1.5v nominal), whether due to internal or external circuitry, invokes a latchoff response and strong discharge of v ing ; hyst is latched low and switching action is inhibited after crowbar overcomes the glitch immunity require - ment (see figure 12). the fast oov comparators output is fed through a blocking pn diode into a 10nf capacitor on the crowbar output; internal circuitry interfacing to crowbar presents itself as a ~10k load (see figure 62 in appendix a ). the use of the pn diode and 10nf capaci - tor creates a way for the crowbar output to stay logic high, even if the duration of oov is very brief, and assures the glitch immunity of the latchoff detection circuitry is overcome. the 10k load and 10nf capacitor provide an upper bound for the duration of time mcb might be on after crowbar activates: 400s, or four time constants. parasitic capacitance on the gate of mcb may increase this time, slightly. observe that when hyst is low, the noninverting input to the fast oov comparator (see appendix a) is clamped by a schottky diode. (when run is low, the noninverting input to the fast oov comparator is clamped by two series schottky diodes.) this differs from when switching ac - tion is engaged, where the noninverting input to the fast oov comparator is normally the v fb signal. therefore, be aware that the crowbar output is nominally inhibited when switching action is inhibited. restarting regulation after a latchoff event has occurred is explained in detail in the start-up/shutdown section. mcb should be placed close to the majority of the load(s)s bulk and mlcc local bypass capacitors. crowbar should be connected to the gate of mcb with a generous signal trace width (20mils, or 0.5mm), to support driving the peak current needed to turn on mcb upon oov detection. at the instant that mcb turns on, it typically draws hundreds of amps from the output capacitors which are mainly located near the load. when mcb turns off, the b-field that may have been built up in the parasitic inductance in the cop - per plane between the output capacitors and mcb cannot vanish instantaneously, and the collapsing of that b-field can induce a negative voltage across the output capacitors and load. closer proximity of mcb to the majority of the output capacitors minimizes this parasitic inductance and hence the resulting magnitude of the negative voltage spike. mcb must be selected according to the following criteria: ? mcb must be a logic-level n-channel mosfet ? the drain-to-source rating of mcb must be greater than the maximum output voltage, v out(peak,oov_detected)
ltm4641 34 4641f applications informationload protection features ? when crowbar goes logic high, the peak drain cur - rent in mcb will be given by v out(peak,oov_detected) / r ds(on) . the peak drain current, and its duration, must not exceed the maximum safe operating area of the mosfet; consult the mosfet vendors data sheet. an upper bound for mcbs on-time is 400s. however, this worst-case conduction time can only happen if the output capacitance on v out is extraordinarily large. the length of time that mcb can possibly conduct ultrahigh drain current is also bounded by 4 ? r ds(on) ? c out(total) . in a majority of applications, output capacitance is low enough that mcb does not conduct ultrahigh drain current for longer than a few microseconds, as seen on the front page. ? mcbs junction temperature must not exceed its specified maximum at any time. consult the mosfet vendors data sheet for device thermal characteristics for single shot thermal transients or single pulse power-handling capability. the peak power sustained by mcb is v out(peak,oov_detected) 2 /r ds(on) . if mcb is used and it is expected that latch will be toggled high (to unlatch the ltm4641) or held logic high continuously (for automatic ltm4641 restart after fault- off), recognize that peak power sustained by mcb during crowbar activity may not be single pulse anymore. therefore, to prevent mcb thermal overstress in such applications, it is recommended to use c tmr to set a rea- sonable cool-down period for the mosfet. additionally, one may opt to implement a circuit that shuts down the ltm4641 when mcb temperature is detected to be too high: a minor modification to figure 47, rt1 would be located as close in proximity to mcb as possible (instead of msp), and r1, r2, and r3 would be experimentally determined. consult the mosfet vendors data sheet for maximum rated junction temperature and device thermal characteristics for repeated pulsed-power transients. when using msp, connect v ing to v ingp and to the gate of msp. see the input capacitors section (earlier) for informa - tion on the input bypassing technique when msp is used. msp must be selected according to the following criteria: ? msp can be either a standard logic or a logic-level n-channel mosfet. ? the drain-to-source breakdown voltage of msp must be greater than the maximum input source voltage. consult the mosfet vendors data sheet and consider temperature effects. ? in order to support very fast turn-on of output volt - age (e.g., sub 1ms ramp up), msp should be turned on quickly to bring up v inh quickly. therefore, a gate input capacitance (c iss ) below 4.7nf is preferred (less is better). ? msp must be able to conduct the maximum input current to the ltm4641s power stage without getting too hot. choose a suitable mosfet package size and r ds(on) that results in reasonable mosfet junction temperature rise. be mindful that i q(vinh) is highest during low line operation. blowing a series-pass input fuse with a crowbaring scr can be an effective overvoltage protection scheme for higher output voltages, e.g., 5v, but a crowbaring mosfet on the output of the converter is more effective at clamping the output voltage. for the same current, the power mosfet will have much less voltage drop than the pn-junction voltage drop of an scr. scr-based circuits involving the ltm4641 are not presented here. evaluation of induced or simulated overvoltage events on a demo board (such as dc1543) is recommended to ensure the end result meets the users expectations. fast output overvoltage comparator threshold o v pgm is nominally biased by internal circuitry to 666mv, according to a 499k and 1m resistor-divider network internal to the ltm4641 driven from the 1v ref . this pin connects directly to the inverting input of the fast oov comparatorsetting the trip threshold that the control-loop-referred feedback voltage, v fb , would have to exceed to result in crowbar becoming logic high. recall that the control-loop pulse frequency modu - lates m top such that v fb is driven to the lesser of the track/ss pin or the bandgap reference voltage of 600mv. when track/ss (and hence, the output voltage) has been fully ramped up, the 666mv on ov pgm represents an oov setting 11% above nominal output voltage. to increase the oov threshold, a resistor can be connected externally from 1v ref to ov pgm ; to decrease the oov threshold, a resistor can be connected externally from
ltm4641 35 4641f applications informationemi performance ovpgm to sgnd. furthermore, the ov pgm trip voltage can be made more accurate than its default setting by paralleling the existing (internal) ov pgm resistor-divider with an external resistor divider comprised of low t.c.r. 0.1%-tolerance resistors, for example. see appendix f for details on how to adjust or tighten the fast oov comparator trip threshold. the switching node: sw pin the sw pin provides access to the midpoint of the power mosfets in ltm4641s power stage. connecting an optional series rc network from sw to gnd can dampen high frequency (~30mhz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. the rc network is called a snubber circuit because it dampens (or snubs) the resonance of the parasitics, at the expense of higher power loss. to use a snubber, choose first how much power to allocate to the task and how much pcb real estate is available to implement the snubber. for example, if pcb space al - lows a low inductance 1w resistor to be usedderated conservatively to 600mw (p snub )then the capacitor in the snubber network (c sw ) is computed by: c sw = p snub v inh(max) 2 ? f sw (30) where v inh(max) is the maximum input voltage that the input to the power stage (v inh ) will see in the application, and f sw is the dc/dc converters full load switching frequency of operation. c sw should be npo, c0g or x7r-type (or better) material. the snubber resistor (r sw ) value is then given by: r sw = 5nh c sw (31) the snubber resistor should be low esl and capable of withstanding the pulsed currents present in snubber cir - cuits. a value between 0.7 and 4.2 is normal. emi performance of ltm4641 (on dc1543) with and with - out a snubber is compared and contrasted in figures?13 to 16. in the examples shown, the snubber networks reduce emi signal amplitude by as much as ~5db. access to sw is also provided to make it possible to deliberately induce a short circuit between the input of ltm4641s power stage (v inh ) and its switch nodeto evaluate, in hardware, the performance of the ltm4641 when a high side mosfet fault condition is simulated. figure 13. radiated emissions scan of ltm4641 producing 5v out at 10a, from 12v in . dc1543 hardware with no snubber network installed. f sw = 550khz. c in(bulk) = 2 10 0 f, c in(mlcc) = 4 10f x7r + 2 4.7f x7r. measured in a 10 meter chamber. quasi-peak detect method figure 14. radiated emissions scan of ltm4641 producing 5v out at 10a, from 12v in . dc1543 hardware with ad hoc snubber network installed directly between sw probe point and gnd, c sw = 10nf, r sw = 1 (1w-rated). f sw = 550khz. c in(bulk) = 2 10 0 f, c in(mlcc) = 4 10f x7r + 2 4.7f x7r. measured in a 10 meter chamber. quasi-peak detect method frequency (mhz) 30 ?10 signal amplitude (db v/m) 0 10 30 en55022 class b limit 40 50 70 4641 f13 20 60 422.4 1010 226.2 618.6 814.8 frequency (mhz) 30 ?10 signal amplitude (db v/m) 0 10 30 en55022 class b limit 40 50 70 4641 f13 20 60 422.4 1010 226.2 618.6 814.8
ltm4641 36 4641f applications informationmultimodule parallel operation for loads that demand more than 10a of load current, multiple ltm4641 devices can be paralleled to provide more output current. see figures 56 and 66 for examples of four or two ltm4641 operating in parallel to deliver 40a or 20a load current, respectively, while providing robust output overvoltage protection. the ltm4641 does not support phase interleaving or clock synchronization, and therefore no ripple-current cancelation effect and no multiplication effect on the output voltage ripple frequency occurs when modules are paral - leled. therefore, it should be anticipated that paralleled applications contain beat frequencies in the output voltage waveform and are contained in the reflected input current. for example, if one module operates freely at 400khz while its paralleled sibling operates freely at 410khz, the conducted emi content will include not only the switching fundamental frequencies400khz and 410khzbut also a beat frequency at the difference of those frequencies, 10khz. the system designer may be motivated to apply an external lc (or pi) filter on the input to each ltm4641 if attenuation of the reflected input currents is desired. the ltm4641 device is a current mode controlled device, so paralleled modules demonstrate good current sharing. this helps equilibrate power losses and reduce thermal differences between paralleled modules. the following pins should be connected to all correspond - ing ltm4641s pin(s) when paralleling ltm4641 outputs: ? v out ? gnd ? v inh ? v inl ? hyst (to synchronize start-up and shutdown) ? track/ss ? comp (to accomplish current sharing) ? crowbar (to syn chronize out put ove rvoltage response) ? latch (to reset all modules after a latchoff event) ? v ing , if msp is used applications informationemi performance frequency (mhz) 30 ?10 signal amplitude (db v/m) 0 10 30 40 50 70 4641 f15 20 60 422.4 1010 226.2 618.6 814.8 frequency (mhz) 30 ?10 signal amplitude (db v/m) 0 10 30 40 50 70 4641 f16 20 60 422.4 1010 226.2 618.6 814.8 figure 15. radiated emissions scan of ltm4641 producing 2.5v out at 10a, from 24v in . dc1543 hardware with no snubber network installed. f sw = 335khz. c in(bulk) = 2 10 0 f, c in(mlcc) = 4 10f x7r + 2 4.7f x7r. measured in a 10 meter chamber. quasi-peak detect method figure 16. radiated emissions scan of ltm4641 producing 2.5v out at 10a, from 24v in . dc1543 hardware with ad hoc snubber network installed directly between sw probe point and gnd, c sw = 2.2nf, r sw = 2.2 (1w rated). f sw = 335khz. c in(bulk) = 2 10 0 f, c in(mlcc) = 4 10f x7r + 2 4.7f x7r. measured in a 10 meter chamber. quasi-peak detect method
ltm4641 37 4641f applications informationmultimode parallel operation ? v osns + , differentially bussed with v osns C ; use gnd shielding ? v osns C , differentially bussed with v osns + ; use gnd shielding ? pgood, if used pulling any one modules run pin low will pull all modules hyst pins low, to cease switching and output voltage regu - lation. when paralleling ltm4641 outputs, each module should have its own r fset resistor locally (if needed) to set the on time (i ion ) consistent with the output voltage set- ting (cf. table?1 and figure 3). customized uvlo settings, latching and nonlatching input overvoltage thresholds, and output overvoltage thresholds need only be configured on one ltm4641. intv cc and drv cc should be connected to each other, separately on each module (see figures 56 and 66)or, if powering drv cc from an auxiliary bias rail, then by applying the technique of figure 51 to each module. if msp is used, only one v ingp need be connected to the gate of msp. the routing of msps source pins to the v inh of all modules may be difficult to accomplish in layout without introducing significant loop area; it may be necessary then to use one msp mosfet on the input to each ltm4641 power stage for practical routing. also, the connections of v osns + and v osns C to multiple modules can be difficult to shield, in practice, so leaving provision for differential-mode filtering of the remote sense signal (c dm1 , c dm2 ) local to each modules remote-sense input pins is advisable. be aware that the loading of the paralleled remote sense amplifiers on the bussed feedback signal alters the equa - tions for setting output voltage as follows. when paralleling n modules, for v out 1.2v, select r set1a not larger than that given by: r set1a = r set1b = v out 0.6v ? 1 ? ? ? ? ? ? s 8.2k n ? ? ? ? ? ? (32) for v out > 1.2v, select r set1a not larger than that given by: r set1a = r set1b = 8.2k n (33) then, determine r set2 by: r set2 = 2 s r set1a v out 0.6 ? n s r set1a 8.2k ? 1 (34) the output voltage setting can be double-checked by: v out = 0.6v 1 + n s r set1a 8.2k + 2 s r set1a r set2 ? ? ? ? ? ? (35) the voltage on the v osns + pins of the modules during regulation become: v vosns + = 0.6v 8.2k n ||r set1a ||r set2 + ? v gnd r set1a ? ? ? ? ? ? ? ? ? ? s r set1a || 16.4k n ? ? ? ? ? ? (36) in multimodule parallel scenarios, v osns C and ?v gnd are still given by equations 12 and 13, respectively. lastly, be aware that the total charge current on the track/ss net will be n ? 1a.
ltm4641 38 4641f applications informationthermal considerations and output current derating thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param- eters defined by jesd51-12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module package mounted to a hardware test board de- fined by jesd51-9 (test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients is found in jesd 51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulators thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd 51-12; these coefficients are quoted or paraphrased below: 1 ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2 jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3 jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4 jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. a graphical representation of the aforementioned thermal resistances is given in figure 17; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance
ltm4641 39 4641f applications informationthermal considerations and output current derating parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator . for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4641, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4641 and the specified pcb with all of the cor - figure 17. graphical representation of jesd51-12 thermal coefficients rect material coefficients along with accurate power loss source definitions; (2) this model simulates a software- defined jedec environment consistent with jsed 51-9 and jesd 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the ltm4641 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled envi- ronment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated jesd51-12-defined values provided in the pin configuration section of this data sheet. the 6v, 3.3v and 1.5v power loss curves in figures 18, 19 and 20 respectively can be used in coordination with the load current derating curves in figures 21 to 42 for calculating an approximate ja thermal resistance for the ltm464 1 with various heat sinking and air fow conditions. these thermal resistances represent demonstrated per - 4641 f17 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance
ltm4641 40 4641f applications informationthermal considerations and output current derating formance of the ltm4641 on dc1543 hardware; a 4-layer fr4 pcb measuring 96mm 87mm 1.6mm using outer and inner copper weights of 2oz and 1oz, respectively. the power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient tem - perature. these approximate factors are listed in table 3. (compute the factor by interpolation, for intermediate temperatures.) the derating curves are plotted with the output current starting at 10a and the ambient temperature at 40c. the output voltages are 6v, 3.3v and 1.5v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal mod - els are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air fow, and with and without a heat sink attached with thermally conductive adhesive tape. the bga heat sinks evaluated in table 7 (and attached to the ltm4641 with thermally conductive adhesive tape listed in table?8) yield very comparable performance in laminar airfow despite being visibly different in construction and form factor. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power while increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operat - ing temperature specifes how much module temperature rise can be allowed. as an example in figure 38, t he load current is derated to ~8a at ~81c ambient with no air or heat sink and the power loss for this 36v in to 1.5v out at 8a out condition is ~3.1w. the 3.74w loss is calculated with the ~3.1w room temperature loss from the 36v in to 1.5v out power loss curve at 8a (figure 20) , and the 1.205 multiplying factor at 81c ambient (interpolating from table 3). if the 81c ambient temperature is subtracted from the 120c junction temperature, then the difference of 39c divided by 3.74w yields a thermal resistance, ja , of 10.4c/win good agreement with table 6. tables 4, 5 and 6 provide equivalent thermal resistances for 6v, 3.3v and 1.5v outputs with and without air fow and heat sinking. the derived thermal resistances in tables 4, 5 and 6 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the effciency curves in the typical per - formance characteristics section and adjusted with the above ambient temperature multiplicative factors. table 3. power loss multiplicative factors vs ambient temperature ambient temperature power loss multiplicative factor up to 40c 1.00 50c 1.05 60c 1.10 70c 1.15 80c 1.20 90c 1.25 100c 1.30 110c 1.35 120c 1.40
ltm4641 41 4641f applications informationthermal considerations and output current derating output current (a) 0 power loss (w) 4 5 6 8 9 4641 f18 3 2 0 2 4 6 1 10 3 5 7 1 8 7 36v in 24v in 12v in figure 18. 6v out power loss, f sw = 660khz at full load, fcb tied to sgnd figure 19. 3.3v out power loss, f sw = 360khz at full load, fcb tied to sgnd figure 20. 1.5v out power loss, f sw = 315khz at full load, fcb tied to sgnd output current (a) 0 power loss (w) 2 4 6 1 3 5 2 4 6 8 4146 f19 10 10 3 5 7 9 36v in 24v in 12v in 6v in output current (a) 0 0 power loss (w) 0.5 1.5 2.0 2.5 6 7 8 9 4.5 4641 f20 1.0 1 2 3 4 5 10 3.0 3.5 4.0 36v in 24v in 12v in 6v in ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f21 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f22 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f23 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm figure 21. 12v in to 6v out , no heat sink, f sw = 660khz at full load figure 24. 12v in to 6v out with heat sink, f sw = 660khz at full load figure 25. 24v in to 6v out with heat sink, f sw = 660khz at full load figure 26. 36v in to 6v out with heat sink, f sw = 660khz at full load figure 22. 24v in to 6v out , no heat sink, f sw = 660khz at full load figure 23. 36v in to 6v out , no heat sink, f sw = 660khz at full load ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f24 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f25 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f26 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm
ltm4641 42 4641f applications informationthermal considerations and output current derating figure 27. 6v in to 3.3v out no heat sink, f sw = 360khz at full load figure 28. 12v in to 3.3v out no heat sink, f sw = 360khz at full load figure 29. 24v in to 3.3v out no heat sink, f sw = 360khz at full load ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f27 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f28 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f29 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm figure 30. 36v in to 3.3v out , no heat sink, f sw = 360khz at full load figure 33. 24v in to 3.3v out with heat sink, f sw = 360khz at full load figure 34. 36v in to 3.3v out with heat sink, f sw = 360khz at full load figure 35. 6v in to 1.5v out no heat sink, f sw = 315khz at full load figure 31. 6v in to 3.3v out , with heat sink, f sw = 360khz at full load figure 32. 12v in to 3.3v out , with heat sink, f sw = 360khz at full load ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f30 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f31 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f32 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f33 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f34 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f35 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm
ltm4641 43 4641f applications informationthermal considerations and output current derating figure 39. 6v in to 1.5v out , with heat sink, f sw = 315khz at full load figure 42. 36v in to 1.5v out with heat sink, f sw = 315khz at full load figure 36. 12v in to 1.5v out no heat sink, f sw = 315khz at full load figure 37. 24v in to 1.5v out no heat sink, f sw = 315khz at full load figure 38. 36v in to 1.5v out no heat sink, f sw = 315khz at full load figure 40. 12v in to 1.5v out , with heat sink, f sw = 315khz at full load figure 41. 24v in to 1.5v out , with heat sink, f sw = 315khz at full load ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f36 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f37 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f38 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f39 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f40 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f41 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm ambient temperature (c) 40 0 maximum load current (a) 1 3 4 5 10 7 60 80 90 4146 f42 2 8 9 6 50 70 100 110 120 400lfm 200lfm 0lfm
ltm4641 44 4641f applications informationthermal considerations and output current derating table 4. 6v output, switching frequency nominally 660khz at full load derating curve v in power loss curve airflow (lfm) heat sink ja (c/w) figure 21 to figure 23 12v, 24v, 36v figure 18 0 none 10.1 figure 21 to figure 23 12v, 24v, 36v figure 18 200 none 8.2 figure 21 to figure 23 12v, 24v, 36v figure 18 400 none 6.8 figure 24 to figure 26 12v, 24v, 36v figure 18 0 bga heat sink 8.1 figure 24 to figure 26 12v, 24v, 36v figure 18 200 bga heat sink 6.5 figure 24 to figure 26 12v, 24v, 36v figure 18 400 bga heat sink 5.5 table 5. 3.3v output, switching frequency nominally 360khz at full load derating curve v in power loss curve airflow (lfm) heat sink ja (c/w) figure 27 to figure 30 6v, 12v, 24v, 36v figure 19 0 none 10.4 figure 27 to figure 30 6v, 12v, 24v, 36v figure 19 200 none 8.4 figure 27 to figure 30 6v, 12v, 24v, 36v figure 19 400 none 7.1 figure 31 to figure 34 6v, 12v, 24v, 36v figure 19 0 bga heat sink 8.6 figure 31 to figure 34 6v, 12v, 24v, 36v figure 19 200 bga heat sink 6.8 figure 31 to figure 34 6v, 12v, 24v, 36v figure 19 400 bga heat sink 5.8 table 6. 1.5v output, switching frequency nominally 315khz at full load derating curve v in power loss curve airflow (lfm) heat sink ja (c/w) figure 35 to figure 38 6v, 12v, 24v, 36v figure 20 0 none 10.3 figure 35 to figure 38 6v, 12v, 24v, 36v figure 20 200 none 8.4 figure 35 to figure 38 6v, 12v, 24v, 36v figure 20 400 none 7.2 figure 39 to figure 42 6v, 12v, 24v, 36v figure 20 0 bga heat sink 9.0 figure 39 to figure 42 6v, 12v, 24v, 36v figure 20 200 bga heat sink 7.0 figure 39 to figure 42 6v, 12v, 24v, 36v figure 20 400 bga heat sink 5.8 table 7. heat sink vendors (with thermally conductive adhesive tape pre-attached) heat sink manufacturer part number website wakefeld engineering ltn20069 www.wakefeld.com aavid thermalloy 375424b00034g www.aavid.com table 8. thermally conductive adhesive tape vendor thermally conductive adhesive tape manufacturer part number website chomerics t411 www.chomerics.com
ltm4641 45 4641f applications informationoutput capacitance table table 9. transient performance (typical values) vs recommended output capacitance. figure 45 and figure 46 circuits c out(mlcc) c out(bulk) v out vendor part number vendor part number 3.3v avx 12106d107mat2a (100f, 6.3v, 1210 case size) 12066d226mat2a (22f, 6.3v, 1206 case size) sanyo poscap 6tpe680mi (680f, 6.3v, 18m esr, d4 case size) taiyo yuden jmk325bj107mm-t (100f, 6.3v, 1210 case size) jmk316bj226ml-t (22f, 6.3v, 1206 case size) tdk c3225x5r0j107mt (100f, 6.3v, 1210 case size) c3216x5r0j226mt (22f, 6.3v, 1206 case size) > 3.3v avx 1206yd226mat2a (22f, 16v, 1206 case size) sanyo poscap 10tpf150ml (150f, 10v, 15m esr, d3l case size) taiyo yuden lmk316bj476ml-t (47f, 10v, 1206 case size) EMK316BJ226ML-T (22f, 16v, 1206 case size) tdk c3216x5r1a476m (47f, 10v, 1206 case size) c3216x5r1c226m (22f, 16v, 1206 case size) v out (v) v in (v) r fset (m) r set1a , r set1b (k) r set2 (k) c in (ceramic) c in * (bulk) c out2 (ceramic) c out1 (bulk) c ffa , c ffb load step slew rate (a/s) transient droop, 0a to 5a load step (mv) transient, peak-to-peak, 0a to 5a to 0a step (mv pk-pk ) recovery time (s) 0.9 5, 12, 24, 36 0.931 4.12 C 2 10f 100f 3 22f 680f C 5 60 130 25 0.9 5, 12, 24, 36 0.931 4.12 C 2 10f 100f 4 100f C C 5 60 140 25 1 5, 12, 24, 36 1.00 5.49 C 2 10f 100f 3 22f 680f C 5 65 135 25 1 5, 12, 24, 36 1.00 5.49 C 2 10f 100f 4 100f C C 5 70 150 25 1.2 5, 12, 24, 36 1.13 8.2 C 2 10f 100f 3 22f 680f C 5 70 140 25 1.2 5, 12, 24, 36 1.13 8.2 C 2 10f 100f 4 100f C C 5 80 170 30 1.5 5, 12, 24, 36 1.43 8.2 33.2 2 10f 100f 3 22f 680f C 5 75 155 30 1.5 5, 12, 24, 36 1.43 8.2 33.2 2 10f 100f 4 100f C 220pf 5 90 190 30 1.8 5, 12, 24, 36 2.00 8.2 16.5 2 10f 100f 3 22f 680f C 5 80 170 40 1.8 5, 12, 24, 36 2.00 8.2 16.5 2 10f 100f 3 100f C 220pf 5 100 215 30 2.5 5, 12, 24, 36 5.76 8.2 7.5 2 10f 100f 3 22f 680f C 5 100 230 50 2.5 5, 12, 24, 36 5.76 8.2 7.5 2 10f 100f 3 100f C 220pf 5 140 290 30 3.3 5, 12, 24, 36 C 8.2 4.7 2 10f 100f 3 22f 680f C 5 140 275 60 3.3 5, 12, 24, 36 C 8.2 4.7 2 10f 100f 3 100f C 100pf 5 200 420 30 5 12, 24, 36 C 8.2 2.61 2 10f 100f 2 22f 150f 220pf 5 220 450 50 5 12, 24, 36 C 8.2 2.61 2 10f 100f 3 47f C 100pf 5 250 570 30 6 12, 24, 36 C 8.2 2.05 2 10f 100f 2 22f 150f 220pf 5 240 500 55 6 12, 24, 36 C 8.2 2.05 2 10f 100f 3 47f C 100pf 5 300 660 30 *bulk capacitance is optional if v in has very low input impedance.
ltm4641 46 4641f applications informationsafety and layout guidance safety considerations the ltm4641 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if fusing is required, a slow blow fuse with a rating twice the maximum input current needs to be provided. the ltm4641 sup - ports overcurrent protection and two kinds of overvoltage protection (see the power good indicator and latching output overvoltage protection section). layout checklist/example the high integration of ltm4641 makes the pcb board layout very straightforward. to optimize its electrical and thermal performance, some layout considerations are necessary. figure 43 and figure 44 show recommended layouts for the circuits shown in figure 45 and figure 46, respectively. ? refer to the following document for device land pattern and stencil design: http://www.linear.com/docs/40146. ? the gerber file for demo board dc1543 can be down - loaded at http://www.linear.com/demo ? use a solid copper gnd plane directly underneath the module. this will help form the return path electrical connections to the input source and output load. it will also provide a thermal path for removing heat from the bga package and minimize junction temperature rise of the ltm4641 for a given application. for consistent ripple and noise from application to application, connect the output gnd plane (the one that conducts load side return current back to the module) and the input gnd plane (the one that conducts module return current back to the input source) underneath the module, only. ? use large pcb copper areas for high current paths, including v inh and v out . ? place high frequency ceramic input and output capaci - tors next to the v inh , gnd and v out pins to minimize high frequency noise. v inh exception: if msp is used, (1) place msp as close to the v inh pins of the ltm4641 as possible and (2) bypass the drain of mspand not v inh to gnd pins of the ltm4641. only one or two high frequency mlccs (c out(mlcc) ) need be placed directly next to the v out and gnd pins of the ltm4641, to minimize high frequency noise close to the source. the majority of c out(mlcc) should be located close to the load to provide high quality bypassing. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly under any pads, unless they are capped or plated over. ? use a separated sgnd ground copper area for compo - nents connecting to signal pins. components connecting to sgnd should be placed as close to the module as possible and routed with minimum trace lengths and trace widths, for best noise immunity. ? note that there are two clusters of sgnd pins on the module: one, formed by pins a1-a3, b1-b3, c1-c4 (a1-quadrant); and a second formed by pins k1, k3, l3, and m1-m3 (m1-quadrant). it is good pcb design practice to provide a copper plane connecting all a1-quadrant sgnd pins together and another plane connecting all m1-quadrant sgnd pins together. it is not necessary to connect these two clusters of sgnd copper planes to each other in the pcb layout, because all sgnd pins are electrically connected to each other internal to the module. ? do not connect the any sgnd pins or sgnd plane(s) to the gnd plane; the electrical star connection is made internal to the module. ? for parallel module operation, see the multimodule parallel operation section for a list of interconnecting pins across paralleled modules. circuit figures?56 and 66 show four and two ltm4641 devices operating in parallel, respectively. route signal-level (non-power) nets on an internal layer, with gnd planes overlapping signal routes to shield them from noise. it is even more effective to surround module-to-module signal connections on the internal layer containing the signal routes with adjacent gnd planes or routes, and periodi- cally punching-through gnd via connections to gnd plane shields on adjacent layers. this practice forms the equivalent of a coaxial cable structure within the pcb, and is highly effective at shielding sensitive signals from noise sources. maintain differential routing of the v osns + /v osns C pin pair.
ltm4641 47 4641f applications informationsafety and layout guidance ? place all feedback components as close to the module as possible, giving layout priority first to capacitors c ffa , c ffb , c cma , c cmb and c dm (if used)followed next by r set1a , r set1b and r set2 (if used). see figure?5 in the applications information section and figure 64 in appendix d for more details. maintain differential routing of the remote-sense lines between the load and the module. form a coaxial cable structure that surrounds the remote-sense lines with gnd potential within the pcb, to the extent that layout permits. see an example of routing the vout/gnd remote-sense pin pair in layer 3 of dc1543. ? to facilitate stuffing verification, and test and debug ac - tivities, consider routing control signals of the ltm4641 with short traces to localized test points, test pads or test viasas pcb layout space permits. both in-house and contract manufacturers enjoy gaining electrical access to all non low impedance (10) pins of an ic or module regulator to improve in-circuit test (ict) coverage. figure 43. recommended pcb layout, figure 45 circuit. view of the ltm4641 from top of package figure 44. recommended pcb layout, figure 46 circuit. view of the ltm4641 from top of package
ltm4641 48 4641f typical applications + r set2 16.4k 4641 f45 r fset 2m c out(mlcc) 47f 10v 6 c in(mlcc) 10f 50v 2 c in(bulk) 50v v in 4v to 38v (4.5v start-up) v out 1.8v 10a local high frequency decoupling r set1a 8.2k r set1b 8.2k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr c ss 4.7nf track/ss v ing v ingp swv inh ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood c tmr n/u sgnd connects to gnd internal to module. keep sgnd routes/planes separate from gnd on motherboard figure 45. 4v in to 38v in , ltm4641 basic configuration, 1.8v output at 10a + r set2 4.7k mcb: nxp psmn5r0-30yl msp: nxp psmn7r0-60ys mcb msp 4641 f46 c in(mlcc) 10f 50v 2 100f 6.3v 3 c in(bulk) 100f 50v 4.5v start-up operation up to 38v in v out 3.3v 10a local high frequency decoupling r set1a 8.2k c ffa 100pf c ffb 100pf r set1b 8.2k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr c ss 22nf track/ss v ing v ingp swv inh ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood sgnd connects to gnd internal to module. keep sgnd routes/planes separate from gnd on motherboard figure 46. ltm4641 delivering 3.3v output at 10a, and providing robust output overvoltage protection from up to 38v in . dropout operation may occur below 4.8v in . see figure 11 to implement custom uvlo rising/falling settings to avoid dropout operation
ltm4641 49 4641f typical applications figure 47. ltm4641 generating 1v output at 10a, surge protected up to 80v in transients. start-up and shutdown waveforms with tmr = intv cc shown in figure 2 figure 48. oscilloscope snap-shot of figure 47 circuit riding through 80v in transient while delivering 1v out at 10a to the load v in 20v/div v inh 20v/div 2ms/div 4641 f48 v out 20mv/div ac-coupled v inl /intv cc /drv cc / latch 5v/div 4.5v start-up operation up to 28v in continuous, transient protected to 80v in + mcb 5v d1 36v 2% r2 8.25k msp r1 20k rt1 ntc 4641 f47 c in(mlcc) 10f 100v 2 100f 6.3v 4 c in(bulk) 100f 100v v out 1v 10a local high frequency decoupling r set1a 5.49k r set1b 5.49k load v osns + v out v inl f set uvlo hyst fcb intv cc drv cc iovretry ovlo run v osns ? v orb + gnd sgnd comp tmr c ss 1nf track/ss v ing r fset 1m r3 2.7m v ingp 5v swv inh ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood c tmr 1f sense r bov 29.4k switching action is temporarily latched off if v in exceeds 80v; autonomous restart attemps occur in 9 second intervals when input voltage returns below 80v. note lt3010-5 is rated for 80v, absolute maximum. see note 1. d2 enables detection of v in uvlo falling msp and switching action are temporarily latched off when a module overtemperature or output overvoltage (oov) condition is detected--additionally, the crowbar mosfet mcb is turned on to protect the load upon oov detection. autonomous restart attempts occur in 9 second intervals when conditions return to normal when v in exceeds ~36v, d1 ensures msp is operated in its linear region and provides rudimentary surge ride-through protection for ltm4641. optional: rt1, r1, r2, r3.to enable rt1?s detection of thermal overstress in msp during sustained input voltage surge events, place rt1 in extremely close proximity to msp in pcb layout. experimentally determine the vaules of r1, r2 and r3 that yield desired overtemperature shutdown inception and restart recovery thresholds consistent with msp?s rated operating junction temperature and safe operating area r rov 4.7m out v in gnd lt ? 3010-5 d2 shdn d2: central semi cmmsh1-100g mcb: nxp psmn5r0-30yl msp: nxp psmn028-100ys rt1: murata ncp15wm474j03rc sgnd connects to gnd internal to module. keep sgnd routes/planes separate from gnd on motherboard
ltm4641 50 4641f typical applications figure 49. ltm4641 producing 0.9v out at 10a, from 3.3v in , and providing advanced output overvoltage protection. v inl , intv cc , and drv cc biased from a low power auxiliary 5v rail figure 50. oscilloscope snap-shot of figure 49 circuit, 2 load on v out . 3.3v in applied briefly to highlight uvlo rising and falling thresholds v in 1v/div v out 1v/div hyst 5v/div pgood 5v/div 4ms/div 4641 f50 + mcb: nxp ph2625l msp: nxp psmn013-30ll mcb msp 4641 f49 c in(mlcc) 47f 6.3v 2 100f 6.3v 4 c in(bulk) 3.3v in nominal 3v in rising start-up 2.3v in falling shutdown 5v low power bias <50ma peak v out 0.9v 10a local high frequency decoupling r set1a 4.12k r set1b 4.12k r fset 360k r hyst 1m r buv 30.9k 100k r tuv 150k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run v osns ? v orb + fcb hyst uvlo gnd sgnd comp tmr c ss 4.7nf track/ss v ing v ingp swv inh ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood sgnd connects to gnd internal to module, keep sgnd routes/planes separate from gnd on motherboard
ltm4641 51 4641f typical applications figure 51. over-driving intv cc /drv cc to reduce v inl -to-intv cc linear regulator losses (cf. figures 52 to 54) figure 52. thermal image of u1 from figure 51 circuit. delivering 5v out at 10a from 36v in , with intv cc connected to drv cc and d1c = open and d2 = open. t a = 25c, bench testing, no airflow figure 53. thermal image of u1 from figure 51 circuit. delivering 6v out at 10a from 36v in , with intv cc connected to drv cc and d1c = open and d2 = open. t a = 25c, bench testing, no airflow figure 54. thermal image of u1 from figure 51 circuit. delivering 5v out at 10a from 36v in , with 5v out feeding intv cc /drv cc through d1c diode. t a = 25c, bench testing, no airflow figure 55. thermal image of u1 from figure 51 circuit. delivering 6v out at 10a from 36v in , with 6v out feeding intv cc /drv cc through d1c diode. t a = 25c, bench testing, no airflow + r set2 ~2.05k to 2.61k 4641 f51 c in(mlcc) 10f 50v 2 v in 8.5v to 38v (10v start-up) c vinl 0.1f 50v c drvcc 2.2f c out(mlcc) 47f 10v 2 c out(bulk) 150f 10v ldo losses in the ltm4641 can be greatly reduced when an auxilliary ~5v to 6v source (v aux ) is available to drive drv cc through a schottky diode as shown (d1c). when ltm4641 is con?gured to produce ~5v out to 6v out , its output can be v aux . provide a current path to v inl from v in and intv cc /drv cc whenever overdriving intv cc /drv cc with v aux ?accomplished here with d1a and d1b c in(bulk) ~5v out to 6v out up to 10a r set1a 8.2k r set1b 8.2k r hyst 1m r buv 15.8k r tuv 294k load v osns + v out v inl a d1 d2 d1, d2: central semi cmksh2-4lr sot-363 package c b v aux f set intv cc drv cc iovretry ovlo run v osns ? v orb + fcb hyst uvlo gnd sgnd comp tmr c ss 47nf track/ss v ing v ingp swv inh ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood sgnd connects to gnd internal to module, keep sgnd routes/planes separate from gnd on motherboard
ltm4641 52 4641f typical applications figure 56: 1v, 40a fault-protected load powered by four parallel ltm4641from up to 38v in . cf. figure 57 r fset1 750k 4.5v in start-up operation up to 38v and down to 4v c mlcc(out) 100f 6.3v 12 c in(mlcc) 10f 50v 4 c in(bulk) 100f 50v 2 v out 1v 40a local high frequency decoupling r set1a 1.37k c ff1 100pf c ff2 100pf r set1b 1.37k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run run enable latchoff reset pull latch normally low for latchoff response to output overvoltage and over- temperature events. pull latch high to restart 1v output alternatively, connect latch to intv cc and install c tmr1 , c tmr2 , c tmr3 and c tmr4 to set 1v output for timed autonomous restart after fault shutdown events mcb: nxp psmn5r0-30yl msp: nxp psmn3r0-60bs fault indicator c ss 22nf c tmr1 n/u v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp msp mcb v inh u1 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 1 1 1 1 1 1 sw c dm1 10pf r fset2 750k v osns + v out v inl f set intv cc drv cc iovretry ovlo run c tmr2 n/u v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u2 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 2 2 2 2 2 sw c dm2 10pf to system p (optional) r fset3 750k v osns + v out v inl f set intv cc drv cc iovretry ovlo run c tmr3 n/u v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u3 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 3 3 3 3 3 sw c dm3 10pf r fset4 750k v osns + v out v inl f set intv cc drv cc iovretry ovlo run c tmr4 n/u v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u4 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 4 4 4641 f56 4 4 4 sw c dm4 10pf u1, u2, u3 and u4 sgnd ( 1 , 2 , 3 , 4 ) connect to gnd internal to their respective modules. keep module sgnd routes/planes separate from other modules and from gnd on motherboard
ltm4641 53 4641f typical applications figure 57: current-sharing performance of four paralleled ltm4641. figure 56 circuit, operating at 28v in total output current (a) 0 8 10 12 32 4641 f57 6 module output current (a) 4 8 16 24 40 2 0 ?2 u1 output current u2 output current u3 output current u4 output current figure 58. negative output application. delivering C5.2v out at up to 10a, from up to 32.8v in . cf. figure 59 figure 59. pulsed application of v in . figure 58 circuit with 500 load. *ultralow v f of d1 minimizes v out overshoot upon energization c in(mlcc) 10f 50v 4 c out(mlcc) 47f 10v 4 c in(bulk) 50v operation up to 32.8v in 4.5v start-up local high frequency decoupling for more information about configuring step-down buck converters as buck-boost converters, for generating negative v out , see http://www.linear.com/docs/39881 r set1a 8.2k r set1b 8.2k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run c ss 10nf v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u1 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood sw r set2 2.46k 100k d1: central semi cmpsh1-4le sgnd connects to gnd internal to module, keep sgnd routes/planes separate from gnd on motherboard d1 v out ?5.2v at up to 10a 4641 f58 + v in 10v/div hyst 2v/div pgood 2v/div v out 2v/div 20ms/div 4641 f59 *
ltm4641 54 4641f typical applications figure 60. fault-protected load with power supply management. ltm4641s fast output overvoltage latchoff trip threshold remains consistently 11% above ltc2978-commanded target v out , even as v out is margined via i 2 c figure 61. ltm4641s v out margined high/low by ltc2978 via i 2 c commands. figure 60 circuit. 12v in . vout_command (0x21) = 1.20v, vout_margin_high (0x25) = 1.32v, vout_margin_low (0x26) = 1.08v v out 200mv/div v dacpo 500mv/div sda, scl 2v/div 20ms/div 4641 f61a v out 200mv/div v dacpo 500mv/div sda, scl 2v/div 20ms/div 4641 f61b v out 200mv/div v dacpo 500mv/div sda, scl 2v/div 20ms/div 4641 f61c v out 200mv/div v dacpo 500mv/div sda, scl 2v/div 20ms/div 4641 f61d (61a) pmbus operation (reg. 0x01): 0x80 0xa8 (margin high) (61b) pmbus operation (reg. 0x01): 0xa8 0x80 (margin off) (61c) pmbus operation (reg. 0x01): 0x80 0x98 (margin low) (61d) pmbus operation (reg. 0x01): 0x98 0x80 (margin off) r fset 1.13m 100f 6.3v 4 c in(mlcc) 22f 25v 2 c in(bulk) 100f 25v 4.5v < v in < 15v additional fault indicator v out 1.2v nominal up to 10a output local high frequency decoupling msp: nxp psmn017-30ll mcb: nxp psmn5r0-30yl ltm4641 sgnd connects to gnd internal to module. keep sgnd routes/planes separate from gnd on motherboard r set1a 8.2k r set1b 8.2k r30 35.7k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run c ss 4.7nf * only one of eight ltc2978 channels shown. ltc2978 pull-ups, bypassing components, and some pins not shown. for details of ltc2978 implementation, see ltc2978 data sheet ** ltc2978 may be powered from either an external 3.3v supply or the system bus ? v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp msp mcb latchoff reset v inh ltm4641* crowbar latch v orb ? temp 1v ref ovpgm otbh pgood sw v dd33 v in_en wp sda scl alert control0 3.3v ? write protect to upstream system enable pmbus interface v out_en0 pwrgd wdi/reset watchdog timer interrupt to p reset input v dacpo v sensepo v sensemo v dacmo v in_sns v pwr asel1 gnd aselo ltc2978** faultoo share_clk to/from other ltc2978s +
ltm4641 55 4641f appendices appendix a. functional block diagram and features quick reference guide figure 62. functional block diagram m hyst 0.5v iuv iovr 10k 499k 10k 3.48k ntc temp otbh tmr latch ovlo iovretry hyst uvlo r hyst 66.5k 1v ref 12.1k 1m r tuv r tov r mov r bov v in v in r buv intv cc por/timeout circuit output optional programming of input undervoltage lockout and hystersis optional programming of nonlatching and latching input overvoltage (ov) thresholds analog temperature output indicator and overtemperature (ot) protection optional programmable power-on reset and timeout delay time input and output ov and ot latch reset internal control loop compensation 5.3v internal v cc ldo off of v inl output voltage power good indicator fet driver bias input output enable pin >2v or floating = on <0.8v = off recommended soft-start or rail tracking optional adjustment of output overvoltage threshold (default internal setting: 11% above nominal) optional pulse-skipping operation for light load ef?ciency programmable ot shutdown behavior: latchoff vs hysteretic restart por/timeout delay timer circuit fast output overvoltage comparator remote sense differential ampli?er optional output protection crowbar n-ch logic-level mosfet optional power rc snubber for reduced emi high current path: input to smps dc/dc converter stage optional series pass electronic ?circuit breaker? n-ch protection mosfet low current path: power control and logic bias input on-time and switching frequency adjustment required for v out 3v, rail tracking applications and when v inl v inh 10v bias (v gs ) charge pump and discharge path for optional external series pass n-ch fet differential sense feedback path with redundant readback pins 666mv nom to v ing pull-down + ? + ? iov + ? ot + ? druv + ? + ? set q rst set q rst osc* ref* fcb comp pgood ss/track 1v ref ov pgm run c ss drv cc intv cc c tmr 4f set q rst oov 100pf mcb 1.5m 10nf 47pf 1k internal comp 499k r tovpgm r bovpgm c ovpgm 10k r sw c sw 8.2k 8.2k v osns ? v orb ? crowbar sgnd v orb + v osns + r set1b r set1a 4641 f62 1m *osc, ref, comparators, op amps and digital gates shown operate from intv cc /sgnd rails sgnd connects to gnd internal to module, keep sgnd routes/planes separate from gnd on motherboard enable switching action power control to e/a 600mv ref (v fb ) constant on-time valley mode synchronous buck controller 8.2k 8.2k r set2 + ? gnd sw v out v inh v ingp v ing v inl 15v zener i out c out(bulk) c out(mlcc) v out 0.6v to 6v up to 10a v in 4v to 38v (4.5v start-up) 10f 2.2f m top m bot 0.8h msp i on + 0.1f c in(mlcc) c in(bulk) 1.3m v ing turn-on charge pump and fault/shutdown discharge circuitry r fset + v out = 0.6v 1 + n r set1a 8.2k ? + 2 ? r set1a r set2 ? ? ? ? ? ? * * * * * * * * * * * use r set1a = r set1 8.2k r set2 required for v out > 1.2v r set2 not necessary for v out 1.2v n = number of modules operaing in parallel (see figure 66 for example of n = 2 and figure 56 for example of n = 4.)
ltm4641 56 4641f appendices appendix b. start-up/shutdown state diagram figure 63. start-up/shutdown state diagram ltm4641 shut down: housekeeping and control sections are unbiased; power stage is off; v ing is discharged intv cc > 2v, nom intv cc < 2v, nom intv cc < 2v, nom intv cc > 2v, nom and latch = low timeout period becomes reset intv cc < 2v, nom ltm4641 housekeeping alive and inhibiting switching action: hyst is pulled low (m hyst is on); power stage is off; v ing is discharged ltm4641 power stage switching action is on: m hyst is off; v ing is charge pumped above v inh ; control loop regulates v out ltm4641 latchoff condition detected: hyst is latched low (m hyst is on); power stage is off; v ing is discharged ltm4641 primed to regulate: waiting only for run pin to transistion high and intv cc to exceed 3.6v nom ; switching action not inhibited by housekeeping circuitry (m hyst is off); power stage is off; v ing is discharged ltm4641 verification of timeout period expiration: housekeeping circuitry holds hyst low (m hyst is on) until and unless the uvlo/iovretry/ ovlo/crowbar/temp/drv cc monitor outputs remain clear for the full duration of the timeout period, as set by tmr pin (c tmr ); power stage is off; v ing is discharged intv cc > 2v, nom; and any of the following nonlatching conditons appear: 1. custom uvlo input too low (v ulvo < uvov th , ~0.5v th ) 2. nonlatching input overvoltage (v iovretry > uvov th , ~0.5v th ) 3. drv cc too low (v drvcc < drv cc(uvlo_rising) , ~3.9v th ) 4. nonlatching overtemperature (otbh = open circuit and v temp < ot th(recover) , ~514mv th ) and no latchoff faults are present: 1. input voltage o.k. (v ovlo < uvov th , ~0.5v th ) 2. crowbar o.k. (v crowbar < v crowbar(th) , ~1.5v th ) 3. temperature o.k. (otbh = low and v temp > ot th(recover) , ~514mv th ) intv cc > 2v, nom; and any of the following nonlatching conditons appear: 1. custom uvlo input too low (v uvlo < uvov th , ~0.5v th ) 2. nonlatching input overvoltage (v iovretry > uvov th , ~0.5v th ) 3. drv cc too low (v drvcc < drv cc(uvlo_falling) , ~3.35v th ) 4. nonlatching overtemperature (otbh = open circuit and v temp < ot th(inception) , ~438mv th ) and no latchoff faults are present: 1. input voltage o.k. (v ovlo < uvov th , ~0.5v th ) 2. crowbar o.k. (v crowbar < v crowbar(th) , ~1.5v th ) 3. temperature o.k. (otbh = low and v temp > ot th(inception) , ~438mv th ) intv cc > 2v, nom; and all of the following fault free conditions are present (or recently appeared, exiting latchoff): 1. custom uvlo input o.k. (v uvlo > uvov th , ~0.5v th ) 2. no input overvoltage(s) (v iovretry < uvov th and v ovlo < uvov th , ~0.5v th ) 3. crowbar inactive (v crowbar < v crowbar(th) , ~1.5v th ) 4. temperature o.k. (v temp > ot th(recover) , ~514mv th ) 5. drv cc above its uvlo (v drv cc > drv cc(uvlo_rising) , ~4.05v th ) intv cc < 2v, nom intv cc < 2v, nom intv cc < 2v, nom 4641 f63 uvlo/iovretry/ovlo/crowbar/temp/drv cc monitor outputs have remained clear for the full duration of the timeout period intv cc > 2v, nom and latch = low intv cc > 2v, nom and any of the following latchoff faults are present: 1. latchoff input overvoltage (v ovlo > uvov th , ~0.5v th ) 2. crowbar active (v crowbar > v crowbar(th) , ~1.5v th ) 3. latchoff overtemperature (otbh = low and v temp < ot th(inception) , ~438mv th ) intv cc > 2v, nom and any latchoff faults are present: 1. latchoff input overvoltage (v ovlo > uvov th , ~0.5v th ) 2. crowbar active (v crowbar > v crowbar(th) , ~1.5v th ) 3. latchoff overtemperature (otbh = low and v temp < ot th(recover) , ~514mv th ) intv cc > 3.2v, nom and all of the following fault free conditions are present: 1. custom uvlo input o.k. (v uvlo > uvov th , ~0.5v th ) 2. no input overvoltage(s) (v iovretry < uvov th and v ovlo < uvov th , ~0.5v th ) 3. crowbar inactive (v crowbar < v crowbar(th) , ~1.5v th ) 4. temperature o.k. (v temp > ot th(inception) , ~438mv th ) 5. drv cc above its uvlo (v drvcc > drv cc(uvlo_falling) , ~3.35v th ) 6. run > v run(on) (2v th , max) intv cc > 3.9v, nom and all of the following fault free conditions are present: 1. custom uvlo input o.k. (v uvlo > uvov th , ~0.5v th ) 2. no input overvoltage(s) (v iovretry < uvov th and v ovlo < uvov th , ~0.5v th ) 3. crowbar inactive (v crowbar < v crowbar(th) , ~1.5v th ) 4. temperature o.k. (v temp > ot th(recover) , ~514mv th ) 5. drv cc above its uvlo (v drv cc > drv cc(uvlo_rising) , ~4.05v th ) 6. run > v run(on) (2v th , max) either intv cc > 3.2v nom and run = low (0.8v th , min)? or 2v < intv cc < 3.2v, nom? and additionally, in either case, all of the following fault free conditions exist: 1. custom uvlo input o.k. (v uvlo > uvov th , ~0.5v th ) 2. no input overvoltage(s) (v iovretry < uvov th and v ovlo < uvov th , ~0.5v th ) 3. crowbar inactive (v crowbar < v crowbar(th) , ~1.5v th ) 4. temperature o.k. (v temp > ot th(recover) , ~514mv th ) 5. drv cc above its uvlo (v drv cc > drv cc(uvlo_falling) , ~3.35v th ) latchoff is cleared when intv cc > 2v, nom and latch toggles from logic low to high and no latchoff faults are present: 1. input voltage o.k. (v ovlo < uvov th , ~0.5v th ) 2. crowbar o.k. (v crowbar < v crowbar(th) , ~1.5v th ) 3. temperature o.k. (otbh = low and v temp > ot th(recover) , ~514mv th ) ltm4641 timeout delay imposed during latchoff: housekeeping circuitry holds hyst low (m hyst is on) until and unless all latchoff fault-monitor outputs remain clear for the full duration of the timeout period, as set by tmr pin (c tmr ) intv cc > 2v, nom and latch = high and any latchoff fault is present: 1. input overvoltage (v ovlo > uvov th , ~0.5v th ) 2. crowbar active (v crowbar > v crowbar(th) , ~1.5v th ) 3. latchoff overtemperature (otbh = low and v temp < ot th(recover) , ~514mv th ) latchoff is cleared when intv cc > 2v, nom and latch = high and all latchoff fault-monitor outputs remain operationally valid for the full duration of the timeout period: 1. input voltage o.k. (v ovlo < uvov th , ~0.5v<) 2. crowbar o.k. (v crowbar < v crowbar(th) , ~1.5v th ) 3. temperature o.k. (otbh = low and v temp > ot th(recover) , ~514mv th )
ltm4641 57 4641f appendices appendix c. switching frequency considerations and usage of r fset there exist many scenarios in which a resistor, r fset , should be connected externally to ltm4641s f set pinto decrease the on-time of m top : most commonly, when the output voltage setting is less than or equal to 3v, and in rail-tracking applications; and less commonly, when v inl and v inh are operating from different source supplies. in the former cases, r fset is usually applied from f set to v inl (figure 45 and front page application circuit); in the latter, r fset is usually applied from f set to the voltage source feeding ltm4641s power stageupstream of msp, if a power-interrupt input mosfet is used (figure?49). there are several motivations and considerations behind this guidance: (1) inherent to ltm4641s constant on-time ar chitec - ture, the switching frequency of ltm4641 decreases as output voltage decreases. in order to maintain a reasonable output capacitor value solution size and output voltage rippleeven at lower output voltages (3v out )r fset should be applied, so that the control - lers i on pin current and the resulting nominal switching frequency is higher than the on-time dictated by the internal v inl -to-f set -connected 1.3m resistor. (2) the pfm control scheme employed by ltm4641 yields a switching frequency at zero load current (no-load operation) that is typically 20% to 25% lower than what it is at full load. as a result, inductor ripple cur - rent is proportionally higher at no load than what it is at heavy load. recall that ltm4641 employs r ds(on) current sensing; furthermore, realize that it is essential for the controllers current-sense amplifier to be able to perceive and command sufficiently negative inductor trough current, enough to maintain a maximum average inductor current of 0a, so that output voltage can be properly regulated down to no load. a value of r fset should be used to assure that switching frequency is high enough (or on-time is small enough) at no load so that the current-sense information representing the trough of choke current is never too large in ampli - tude. figure 3 provides conservative guidance on the maximum value of r fset (or equivalently, the minimum i on current) that assures proper no-load operation. (3) in rail-tracking applications, ltm4641s output voltage must track a reference voltage not only during v out ramp up but also during v out ramp down; fulfilling the latter requires ltm4641 to sink current from the output capacitors. a value of r fset should be used that assures the output voltage can be ramped down to ones minimum desired output voltage of regula - tionnot just the intended nominal output voltage. figure 3 provides this guidance. (4) in order to maintain a relatively constant switching frequency for a given output voltage (across the full line voltage), the on-time of m top should be inversely proportional to the voltage source feeding the v inh power stageupstream of msp, if a power-interrupt mosfet is used (figure 46). when v inl and v inh are operated from different rails, this goal can be accom - plished satisfactorily by placing r fset between f set and the power v in input source (see figure 49: the connection is to v in and not v inl , and usually not v inh , but see a counterexample in figure?47 and explana - tion in item number 5 of this list). a minor error term to the on-time is introduced by the internal 1.3m v inl -to-f set -connected resistor in such scenarios, so calculation of i ion at all operating input voltage corner cases (power, v inh and control bias, v inl extremes) and the resulting switching frequency range of opera - tion, given by equation 6, should be considered. (5) when msp is used, and when v inl and v inh are operated from different railshere is the reason it is recommended to connect r fset from f set to the drain of msp rather than v inh : prior to start-up, msp is off, and v inh is discharged. connecting r fset to v inh would set the on-time at the instant switching activity commenced to be much lower than intended. the on-time would not reach its final settling value until v ing circuitry had turned on msp enough for v inh to become pulled up to v in potential. it should become apparent that a mechanism may exist for dynamic interaction between how rapidly the output voltage ramps up (depending on track/ss pin usage) versus how rapidly msp might turn on. we know from item number 2 of this list that on-time should not be arbitrarily large. in general, to avoid any undesirable
ltm4641 58 4641f appendices interactionswhich might at worst result in exces- sive output voltage ripple or non-monotonic output voltage ramp-up, a sufficiently slow output voltage ramp-up time can eliminate the danger of v inh and on-time settling interactions influencing output volt - age ripplebut properly, this requires investigation and hardware evaluation on a case-by-case basis. figure?47 shows an example where r fset connects between f set and v inh rather than the input source supply. because msp limits the v inh voltage during the input voltage surge, the correct i on programming current can only be made with a resistor interface to v inh , in that example. appendix d. remote sensing in harsh environments the rationale for using the symmetrical resistor network is to provide a consistent feedback structure that enables fully differential remote-sense of output voltages between 0.6v and 6v with the flexibility to filter differential and common mode noise in harsh environments. see figure?64. the use of not greater than 8.2k nominal resistors for r set1a (and r set1b ) assures that the remote-sense signal is not attenuated at frequencies of interest by the pole formed by the feedback resistors and parasitic capacitances. fur - thermore, using an r set1a (and r set1b ) value of 8.2k for 1.2v out and larger assures that the common mode range of the remote-sense pins is within their valid range of C0.3v, minimum, to 3v, maximumeven if voltage drop between the modules ground deviates from the pols ground by as much as 0.6v. the differential remote-sense feedback signal is routed from the load as a differential pair on pcb traces (or twisted pair, if wires are used) to r set1a /r set1b feedback components. it is very important to place r set1a /r set1b and all other components forming the feedback impedance- divider network as close to ltm4641 as is possible. ground shielding of the differential remote-sense signal is strongly recommended, to prevent stray noise from contaminating the feedback information. if good shielding of the feedback signals cannot be pro - vided, it is proactive to leave space in ones layout for a small filter capacitor, c dm , placed directly between v osns + and v osns C , as close to the pins of the module as pos - siblein anticipation of the possible need to attenuate differential mode noise. finally, if the pol is very far from the ltm4641, such as: the output power connection (v out and gnd) is made figure 64. feedback remote sense connections and techniques for harshest operating environments + ? + 8.2k v osns + v osns ? v orb + v orb ? sgnd ict test point v out c out(bulk) c out(mlcc) r set2 r set1a c cma c ffb c ffa ict test point 4641 f064 place all feedback components local to the ltm4641 v fb to error amplifier 8.2k 8.2k 8.2k ltm4641 true differential remote sense amplifier gnd v out r set1b route feedback signals as a differential pair (or twisted pair if using wires). sandwich between ground planes to form a protective shield, guarding against stray noise c dm c cmb load c ffa , c ffb : feedforward capacitors yeild improved transient response when filtering v out with only mlcc output capacitors (c out(mlcc) ) c cma , c cmb : if appreciable cable length connects the ltm4641?s output to the load (e.g., through several feet of wire), leave provision for high frequency decoupling of common mode ground noise with these capacitors. these are not needed in purely pcb-based designs, where the ltm4641 is close to the load if effective ground shielding of the feedback signals cannot be implemented, leave provision for a small capacitor (c dm ) to attenuate differential mode noise if necessary sgnd connects to gnd internal to module. keep sgnd routes/planes separate from gnd on motherboard
ltm4641 59 4641f appendices through a board-to-board connector; an inductive length of cable (say, 50cm in length, or more); or, if the load is highly inductivethen it is proactive to leave provision in ones layout for a pair of small filter capacitors, c cma and c cmb . c cma and c cmb should be placed directly from v osns + to sgnd and v osns C to sgnd, respectivelyas close to the pins of the module as possible. configured in this manner, c cma and c cmb can be used to attenuate common mode noise in the remote-sense signal pin pair. appendix e. inspiration for pulse-skipping mode operation when m top is turned onfor a duration of time propor - tional to i ion currentinductor current is ramped upwards, and energy is built up in the inductors b-field. ultimately, a packet of energy is transferred from the input capaci - tors to the output capacitors. in forced continuous mode operation (fcb logic low), m top and m bot are operated in a purely synchronous fashion, meaning: when m top is on, m bot is offand vice versa. observe that when m top is turned off, the b-field in the inductor cannot instantaneously vanish: the collapsing b-field forces inductor current to flow through m bot s on-die schottky dioderesulting in unwanted freewheeling diode power loss; m bot is turned on for lower power loss, instead. with m bot on, inductor current ramps downward as energy in its b-field wanes. in steady-state forced continuous mode operation, the inductor ripple current appears as a triangle waveform whose average value equates to the loads current. forced continuous mode operation (forcing synchronous opera - tion of m top and m bot ) provides a mechanism for consis - tent output voltage ripple, regardless of the load current. however, in this mode of operation, at light load currents (say, less than 2a out), observe that the inductor current is periodically negativewhich means some packets of energy that are transferred from the input capacitors to the output are recirculated and transferred back to the input capacitors. this is a source of inefficiency that brings about the motivation for pulse-skipping mode operation, to turn off m bot when the inductor current ramps down to 0a. this concept is also described in the industry as diode emulation, because m bot is made to mimic the behavior of a schottky rectifier. in pulse-skipping mode operation (fcb logic high), the inductor ripple current at light loads appears as an asymmetrical truncated triangle waveform; inductor current does not go below 0a. appendix f. adjusting the fast output overvoltage comparator threshold the output overvoltage inception threshold (ov pgm volt- age) can be adjusted or tightened from its default value. the following guidelines must be followed, however: ? it is not recommended to change the ov pgm voltage dynamically because the fast oov comparator has no glitch immunity beyond what is provided by ov pgm s internal 47pf capacitor, and routing of ov pgm can make it vulnerable to electrostatic noise. ? the 15.6s time constant filter formed by ov pgm s in - ternal 47pf capacitor and default 499k||1m resistor- divider network should be maintained for practical values of ov pgm voltage: 0.6v < v ovpgm < 0.9v. capacitive filtering of ov pgm must not be applied indiscriminately. the ov pgm voltage must come up very rapidly with the 1v ref at start-up, to prevent a race condition that would otherwise result in nuisance oov detection and a faulty latchoff eventso any externally applied capacitance cannot be arbitrarily high. on the other hand, ov pgm must have some filtering from switching noise sources and should be sufficiently insulated from any possible dynamic activity on 1v ref . (see figure 9.) ? external resistor(s) applied between ov pgm and 1v ref / sgnd should be relatively high impedance, to minimize loading on the 1v ref output. then, small values of c ovpgm achieve a consistent time constant as ovpgms resistance-divider network is altered. figure 65 shows the optional network one can apply to alter or tighten the ov pgm setpoint. figure 65. optional ov pgm network to alter or tighten v ovpgm r tovpgm r bovpgm 4641 f65 c ovpgm 1v ref ov pgm sgnd ltm4641
ltm4641 60 4641f appendices to nudge the ov pgm setpoint downward, to a new oov inception threshold voltage at ov pgm(new) using an r bovpgm resistor, onlycalculate: r bovpgm = 1 1v ? ov pgm(new) ov pgm(new) ? 499k ? 1 1m (37) the new ov pgm threshold can then be double-checked by ov pgm(new) = 1v ? 1m ||r bovpgm ( ) 499k + 1m ||r bovpgm ( ) (38) when lowering the ov pgm setpoint with application of r bovpgm only, it is not necessary to apply a c ovpgm capacitor, because: for an extreme ovpgm(new) setting of 600mv, which is not practical since that is the voltage of v fb during normal regulation, the time-constant of the ov pgm network would have changed by less than 2s from its default value. to nudge the ov pgm trip threshold upward to set a new oov inception threshold voltage at ov pgm(new) using an r tovpgm resistor onlycalculate: r tovpgm = 1 ov pgm(new) 1v ? ov pgm(new) ( ) ? 1m ? 1 499k (39) the new ov pgm setting can then be double-checked by: ov pgm(new) = 1v ? 1m 499k ||r tovpgm + 1m ( ) (40) if r tovpgm is computed in equation 39 to be smaller than 10k, connect ov pgm to 1v ref and do not apply any c ovpgm capacitor; this will yield an oov setting of 167% of nominal. otherwise, use the next smallest standard value of c ovpgm available, computed by: c ovpgm = 15.6s 499k ||1m ||r tovpgm ( ) ? 47pf (41) the default v ovpgm setpoint is 665mv 2.26%, over temperature. to tighten the ov pgm setpoint, begin by choosing r bovpgm to be a commonly available precision 100k, low t.c.r. resistor. using tolerances of 0.1% and a t.c.r. of 25ppm/c can provide a considerable improvement in accuracy over the default divider network, over temperature. next, decide the new value of v ovpgm desiredov pgm(new) within a practical window of 0.6v < ov pgm(new) < 0.9v. then, compute r tovpgm according to: r tovpgm = 1 ov pgm(new) 1v ? ovp gm(new) ( ) ? 1m ||r bovpgm ( ) ? 1 499k (42) the new ov pgm setting can be double-checked by: ov pgm(new) = 1v ? 1m ||r bovpgm ( ) 499k ||r tovpgm + 1m ||r bovpgm ( ) (43) then, use the next smallest standard value of c ovpgm available, computed by: c ovpgm(new) = 15.6s 499k ||1m ||r tovpgm ||r bovpgm ( ) ? 47pf (44) for example, the ov pgm(new) setpoint can be kept at its nominal value of 666mvbut with better accuracyby using 0.1% precision resistors with 25ppm/c t.c.r. for r bovpgm = 100k and r tovpgm = 49.9k, and bypassing ov pgm to sgnd with c ovpgm = 470pf. the resulting v ovpgm oov setpoint threshold becomes better than 1.8%, over temperature. the vast majority of the remaining variation in the threshold setting comes variation of the 1v ref a 1.5% reference, over temperature. the extreme values of the oov setpoint voltage, plus the ovp err termwhich is the offset voltage of the fast comparator (12mv maximum, over temperature)gives guidance on what the minimum and maximum voltage v fb can be at which the crowbar output would swing logic high and invoke latchoff overvoltage protection. one must take care to set the ov pgm voltage to a practical level and not too aggressively. if ov pgm is set too low, the system will demonstrate nuisance output overvoltage latchoff behavior. the output voltage of any switching
ltm4641 61 4641f appendices regulator can witnesses transient excursions above its ideal dc voltage operating point routinely, owing to: ? control ic bandgap reference accuracy ? output voltage ripple and noise ? load current step-down transient eventsincluding recovery from a short-circuit condition ? steep line voltage step-up ? start-up overshoot (little or no soft-starting of v out ), or rail-tracking a fast master rail the linear technology ltpowercad design tool can help quantify some of these dynamic values; ltm4641s total dc error (including bandgap reference variation) is better than 1.5%, over temperature. if ov pgm has been decreased to its lowest practical level and output voltage overshoot during high side mosfet short-circuit testing (shorting v inh to sw on evaluation hardware such as dc1543, for example) does not clamp the output voltage to ones satisfaction, be aware that increasing output capacitance can reduce the maximum output voltage excursion. the reason follows: the larger the output capacitance, the longer it takes for the output voltage to be ramped up, even in the extreme case of deliberately short circuiting v inh to sw. the capacitance on v out is mainly what prevents the output voltage from shooting up to v inh until crowbar turns on mcb. multimodule parallel applications also have better output voltage overshoot during high side mosfet short-circuit testing, owing to the fact that the sibling modules whose high side mosfets are not short circuited are able to help pull the output voltage down by turning on their low side power mosfets. examples of paralleled ltm4641 power - ing and protecting loads are shown in figures 56 and 66.
62 4641f ltm4641 package description package photo table 10. ltm4641 component bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 sgnd b1 sgnd c1 sgnd d1 v orb + e1 gnd f1 gnd a2 sgnd b2 sgnd c2 sgnd d2 v orb C e2 gnd f2 gnd a3 sgnd b3 sgnd c3 sgnd d3 otbh e3 gnd f3 gnd a4 hyst b4 uvlo c4 sgnd d4 tmr e4 gnd f4 gnd a5 temp b5 ovlo c5 latch d5 run e5 gnd f5 gnd a6 iovretry b6 gnd c6 1v ref d6 gnd e6 gnd f6 gnd a7 gnd b7 gnd c7 gnd d7 gnd e7 gnd f7 gnd a8 gnd b8 gnd c8 gnd d8 gnd e8 gnd f8 gnd a9 gnd b9 crowbar c9 v out d9 v out e9 v out f9 gnd a10 gnd b10 ov pgm c10 v out d10 v out e10 v out f10 gnd a11 gnd b11 gnd c11 v out d11 v out e11 v out f11 gnd a12 gnd b12 gnd c12 v out d12 v out e12 v out f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 v osns + j1 comp k1 sgnd l1 pgood m1 sgnd g2 gnd h2 v osns C j2 f set k2 fcb l2 track/ss m2 sgnd g3 gnd h3 gnd j3 v inl k3 sgnd l3 sgnd m3 sgnd g4 gnd h4 gnd j4 drv cc k4 intv cc l4 gnd m4 gnd g5 gnd h5 gnd j5 gnd k5 gnd l5 gnd m5 gnd g6 gnd h6 gnd j6 gnd k6 gnd l6 gnd m6 gnd g7 gnd h7 gnd j7 gnd k7 v inh l7 v inh m7 v inh g8 gnd h8 gnd j8 gnd k8 v inh l8 v inh m8 v inh g9 gnd h9 gnd j9 gnd k9 v inh l9 v inh m9 v ing g10 gnd h10 sw j10 gnd k10 v inh l10 v inh m10 v ingp g11 gnd h11 gnd j11 gnd k11 gnd l11 v inh m11 v inh g12 gnd h12 gnd j12 gnd k12 gnd l12 v inh m12 v inh
ltm4641 63 4641f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view pin 1 3 see notes suggested pcb layout top view bga 144 0212 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a 0.0000 0.0000 detail a ?b (144 places) d a detail b package side view z m x yzddd m zeee 0.630 0.025 ? 144x e b e e b a2 f g bga package 144-lead (15mm 15mm 5.01mm) (reference ltc dwg # 05-08-1914 rev ?) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 144 // bbb z z h2 h1 0.0 f g h m l j k e a b c d 2 1 4 3 567 12 891011
ltm4641 64 4641f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 1012 ? printed in usa related parts typical application r fset1 750k 4.5v in start-up operation up to 38v and down to 4v c mlcc(out) 100f 6.3v 6 c in(mlcc) 10f 50v 4 c in(bulk) 100f 50v 2 v out 1v 20a local high frequency decoupling r set1a 2.74k c ff1 100pf c ff2 100pf r set1b 2.74k load v osns + v out v inl f set intv cc drv cc iovretry ovlo run run enable latchoff reset pull latch normally low for latchoff response to output overvoltage and over- temperature events. pull latch high to restart 1v output alternatively, connect latch to intv cc and install c tmr1 and c tmr2 to set 1v output for timed autonomous restart after fault shutdown events mcb: nxp psmn5r0-30yl msp: nxp psmn7r0-60ys fault indicator c ss 22nf c tmr1 n/u v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp msp mcb v inh u1 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 1 1 1 1 1 1 sw c dm1 22pf r fset2 750k v osns + v out v inl f set intv cc drv cc iovretry ovlo run c tmr2 n/u v osns ? v orb + uvlo hyst fcb gnd sgnd comp tmr track/ss v ing v ingp v inh u2 ltm4641 crowbar latch v orb ? temp 1v ref ovpgm otbh pgood 2 2 4641 f66 2 2 2 sw c dm2 22pf to system p (optional) 1 , u1 and u2 sgnd ( ) connect to gnd internal to their respective modules. keep module sgnd routes/planes separate from other modules and from gnd on motherboard 2 figure 66. 1v, 20a fault-protected load powered by paralleled ltm4641from up to 38v in . cf. typical performance characteristics part number description comments ltm4620 dual 13a, single 26a module regulator up to 100a with four devices; 4.5v v in 16v; 0.6v v out 2.5v. see ltm4620a for higher v out ; 15mm 15mm 4.41mm lga ltm4613 en55022b certified 36v, 8a step-down module regulator 5v v in 36v; 3.3v v out 15v; synchronizable, parallelable, 15mm 15mm 4.32mm lga ltm4627 20v, 15a step-down module regulator 4.5v v in 20v; 0.6v v out 5v; synchronizable, parallelable, remote sensing, 15mm 15mm 4.32mm lga or 15mm 15mm 4.92mm bga ltm8027 60v, 4a step-down module regulator 4.5v v in 60v; 2.5v v out 24v; synchronizable, 15mm 15mm 4.32mm lga ltm4609 36v, 4a buck-boost module regulator 4.5v v in 36v; 0.8v v out 34v; synchronizable, parallelable, up to 4a in boost mode and 10a in buck mode, 15mm 15mm 2.82mm lga or 15mm 15mm 3.42mm bga lt4356 high voltage surge stopper 100v in overvoltage and overcurrent protection, latchoff and auto-retry options

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